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Dorothy Lukco

Publications and source records attributed to Dorothy Lukco.

17 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2024

Contamination Results of MISSE 8 Wake and Nadir Samples After 2 Years of Space Exposure on the International Space Station

Spacecraft in low Earth orbit (LEO) are subjected to harsh environmental conditions, including radiation (cosmic rays, ultraviolet, x-ray and charged particle radiation), micrometeoroids and orbital debris, temperature extremes, thermal cycling, and atomic oxygen. In addition, on-orbit spacecraft contamination is a serious spaceflight issue, with silicone contamination being a particular concern. In an effort to understand on-orbit contamination of Materials International Space Station Experiment 8 (MISSE 8) flight samples and other International Space Station (ISS) payloads, contamination studies were conducted post-flight on retrieved Teflon fluorinated ethylene propylene (FEP) samples flown in the wake and nadir orientations on MISSE 8. The wake sample was Teflon FEP (M8-W11) flown as part of the Glenn MISSE 8 Polymers Experiment on the Optical Reflector Materials Experiment-III Ram/Wake (ORMatE-III R/W) tray and exposed to the LEO wake environment for 2.0 years. The nadir samples were silver-Teflon FEP radiator pieces taken from the MISSE 8 Single Events Upset Xilinx-Sandia Experiment II (SEUXSE II) Power Box and exposed to the LEO nadir environment for 2.14 years. The Teflon FEP flight materials were analyzed for changes in surface morphology and chemistry as compared to pristine control samples. The wake samples were also analyzed for changes in optical properties. There was no evidence of a molecular contamination layer present on the surface of the MISSE 8 wake or nadir facing Teflon FEP flight samples, although both the wake and nadir flight samples contained particulate contamination in some regions. The analyzed nadir particles were primarily zinc rich. The majority of analyzed wake particles were comprised of oxidized aluminum with small amounts of zinc and magnesium. The wake particles appear to have arrived early in the mission (or pre-flight) during a single event. This paper provides details of the MISSE 8 sample contamination analyses.

Erosion↗
NASA NTRS2024

Analyses of the MISSE 9-15 Polymers and Composites Experiment 1-4 (PCE 1-4) Contamination Samples

Spacecraft in low Earth orbit (LEO) are subjected to harsh environmental conditions, including radiation (cosmic rays, ultraviolet (UV), x-ray and charged particle radiation), micrometeoroids and orbital debris, temperature extremes, thermal cycling, and atomic oxygen (AO). These environmental exposures can result in erosion, embrittlement and optical property degradation of susceptible materials threatening spacecraft performance and durability. To increase our understanding of environmental effects such as AO erosion and radiation induced embrittlement of spacecraft materials, NASA Glenn Research Center developed a series of experiments that were flown as part of the Materials International Space Station Experiment (MISSE) missions on the exterior of the International Space Station (ISS). Recently, four Glenn experiments with 365 flight samples were flown on ISS’s MISSE-Flight Facility (MISSE-FF). These experiments are the Polymers and Composites Experiment-1 (PCE-1) flown as part of the MISSE-9 mission, the PCE-2 flown as part of the MISSE-10 mission, the PCE-3 flown as part of the MISSE-12 and MISSE-15 missions, and the PCE-4 flown as part of the MISSE-13 mission. Each of these experiments included passive contamination witness samples in each flight direction for post-flight molecular contamination analyses. A total of 13 contamination flight samples were flown. The post-flight analyses of the PCE 1-4 contamination samples include X-ray Photoelectron Spectroscopy (XPS) analyses (surface and ion sputter depth analyses) and optical properties (total reflectance, total transmittance and solar absorptance). This paper provides results of post-flight analyses of the PCE 1-4 contamination samples and their corresponding control samples. Knowledge of on-orbit contamination is important for the PCE 1-4 flight data interpretation.

Atomic Oxygen↗
NASA NTRS2023

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS2023

Venus Surface Environmental Chamber Test of SiC JFET-R Multi-Chip Circuit Board

This poster describes a first attempt to demonstrate a multi-chip prototype lander control and sensor signal digitization electronics circuit board comprised of ten NASA Glenn IC Generation 11 SiC JFET-R IC chips in 460 °C, 9.4 MPa harsh Venus surface conditions. The lander circuit ceased electrical operation prematurely at 107 °C as the Venus chamber heated up. Optical and SEM post-test inspections indicate fatal dielectric cracks occurred on only one of the ten SiC chips.

silicon carbide↗
NASA NTRS2023

Metal Contact Processing Experiments Towards Realizing 500 °C Durable RF 4H-SiC BJTs

This paper presents results from metal contact processing experiments towards the implementation of durable 500 °C high-frequency 4H-SiC bipolar junction transistors (BJTs) . Specifically, p -type ohmic contacts have been demonstrated on a 0.25 μm-thick p -type homoepitaxial layer of doping 8 x 10 18 ± 4 x 10 18 cm -3 . Preliminary current-voltage characteristics of fabricated BJTs are presented.

4H-SiC BJT↗
NASA NTRS2018

Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions

Prolonged Venus surface missions (lasting months instead of hours) have proven infeasible to date in the absence of a complete suite of electronics able to function for such durations without protection from the planet’s extreme conditions of ~460 °C, ~9.3 MPa (~ 92 Earth atmospheres) chemically reactive environment. Here we report testing data from a successful two-month (60-day) operational demonstration of two 175-transistor 4H-SiC junction field effect transistor (JFET) semiconductor integrated circuits (ICs) directly exposed (no cooling and no protective chip packaging) to a high-fidelity physical and chemical reproduction of Venus surface atmospheric conditions in a test chamber. These results extend the longest reported duration of electronics operation in Venus surface atmospheric conditions almost 3-fold and were accomplished using prototype SiC JFET chips of more than 7-fold increased complexity. The demonstrated advancement marks a significant step towards realization of electronics with sufficient complexity and durability for implementing robotic landers capable of returning months of scientific data from the surface of Venus.

Integrated Circuit↗
NASA NTRS2016

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

JFET↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.

Silicon Carbide↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 µm to 2 µm) coupled with enlarged die size (from 3 x 3 mm to 5 x 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.

silicon carbide↗
NASA NTRSDate not supplied

Early Burn-In Parasitic Conduction in 500 °C Durable SiC JFET ICs

All prior reports of long-term 500 °C operation of SiC JFET-R ICs have noted the existence of an initial “burn-in” period of changes in measured electrical characteristics for the first few hundred hours oven-testing. This work reports measurements of “burn-in parasitic MOSFET conduction” that can substantially impact the performance of some circuits during initial heat-up of JFET ICs, but then subsequently disappears after a few hours of operation at 500 °C. The behavior appears generally consistent with the known MOS phenomenon of bias-temperature driven redistribution of mobile ionic contamination. Approaches for further mitigating this initial burn-in conduction mechanism are discussed.

silicon carbide↗
NASA NTRSDate not supplied

Early Burn-In Parasitic Conduction in 500 °C Durable SiC JFET ICs

All prior reports of long-term 500 °C operation of SiC JFET-R ICs have noted the existence of an initial “burn-in” period of changes in measured electrical characteristics for the first few hundred hours oven-testing. This work reports measurements of “burn-in parasitic MOSFET conduction” that can substantially impact the performance of some circuits during initial heat-up of JFET ICs, but then subsequently disappears after a few hours of operation at 500 °C.

silicon carbide↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRSDate not supplied

VfOx in GEER: Functional Test of a Venus Oxygen Fugacity Sensor

VfOx, which stands for “Venus Oxygen Fugacity” is the DAVINCI mission’s Student Collaboration Experiment (SCE); a small single- objective sensor used to measure the partial pressure of molecular oxygen in Venus’ lower atmosphere. Through the mission timeline, VƒOx will be designed, fabricated, tested, operated, and results analyzed by undergraduate and graduate students mentored by the DAVINCI team in partnership with Johns Hopkins University and other institutions. The simple principal of VƒOx is a ceramic O 2 sensor derived from common applications, utilizing diffusion of O -2 ions between a standard (PdO) inside the sensor and the target atmosphere measured by a mW level voltage that depends directly on the standard/sample fO 2 ratio. A 60-day environmental test of a prototype design of the sensor was conducted at the Glenn Extreme Environment Rig (GEER) from August to October of 2022, in which VƒOx (Fig. 1) was placed inside the experimental chamber (Fig. 2) and brought to Venus surface temperature (460 °C) and pressure (92 bar) conditions, in a Venus like atmosphere (96.5% CO 2 , 3.5% N 2 ) that included trace gases like SO 2 , maintained by occasional “boosts” of extra gas during the experimental run.

Noam R. Izenberg↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRSDate not supplied

Metal Contact Processing Experiments Towards Realizing 500 °C Durable RF 4H-SiC BJTs

This paper presents results from metal contact processing experiments towards the implementationof durable 500 deg.C high-frequency 4H-SiC bipolar junction transistors (BJTs). Specifically, p-type ohmic contacts have been demonstrated on a 0.25 μm-thick p-type homoepitaxial layer of doping 8 x 1018± 4 x 1018cm-3. Finally, preliminary current-voltage characteristics of fabricated BJTs are presented.

RF SiC↗