Engineering topics
Publications and source records attributed to Fang, W. C..
This paper presents a low-power VLSI neural processor that has been developed for high-speed vision processing based upon the frequency-sensitive self-organization (FSO) neural algorithm.
In this paper, an ultra-fast smart vision system-on-a-chip design is proposed to provide effective solutions for real time machine vision applications by taking advantages of recent advances in integrated sensing/processing designs, electronic neural networks, advanced microprocessors and sub-micron VLSI technology.
A low power smart vision system based on a large format (currently 1Kx1K) active pixel sensor (APS) integrated with a programmable neural processor for fast vision applications is presented.
VIGILANTE consists of two major components:1. the Viewing Imager/Gimballed Instrumentation Laboratory (VIGIL)- advanced infrared, visible, and ultraviolet sensors with appropriate optics and camera electronics & 2. the Analog Neural Three-dimensional processing Experiment (ANTE)-a massively parallel, neural network-based, high-speed processor.
A brief history of NASA robotic spacecraft computing architectures is given. Changing needs driving changes in features (10x reduction in cost, various increases in capability, 10x to 100x reduction in power, mass and volume) for spacecraft computing are discussed. A scaleable, parallel/neural computing architecture which addresses these changes is proposed. Evaluation of some of this architecture's components is detailed. Finally, future directions of exploration for this spacecraft computing architecture are considered.
The TELSTAR 4 communication satellites being manufactured by Martin Marietta Astro Space (Astro Space) for AT&T are three axis stabilized spacecraft scheduled to be launched on expendable vehicles such as the Atlas or Ariane rockets. Typically, these spacecraft consist of a box that holds the electronics and supports the antenna reflectors and the solar array wings. The wings and reflectors are folded against the sides of the box during launch and the spacecraft is spun for attitude control in that phase; they are then deployed after achieving the final orbit. The launch phase and transfer orbits required to achieve the final geosynchronous orbit typically take 4 to 5 days during which time the power required for command, telemetry, attitude control, heaters, etc., is provided by two 50 AH nickel hydrogen batteries augmented by the exposed outboard solar panels. In the past, this situation has presented no problem since there was a considerable excess of power available from the array. In the case of large high powered spacecraft such as TELSTAR 4, however, the design power levels in transfer orbit approach the time-averaged power available from the exposed surface area of the solar arrays, resulting in a very tight power margin. To compound the difficulty, the array output of the spinning spacecraft in transfer orbit is shaped like a full wave rectified sine function and provides very low charging rates to the batteries during portions of the rotation. In view of the typically low charging efficiency of alkaline nickel batteries at low rates, it was decided to measure the efficiency during a simulation of the TELSTAR 4 conditions at the expected power levels and temperatures on three nickel hydrogen cells of similar design. The unique feature of nickel hydrogen cells that makes the continuous measurement of efficiency possible is that hydrogen is one of the active materials and thus, cell pressure is a direct measure of the state of charge or available capacity. The pressure is measured with a calibrated strain gage mounted on the outside of the pressurized cell.
A lightweight, low-power, real-time data compressor design for the Earth Observing System (Eos) onboard synthetic aperture radar (SAR) processor is presented. The implementation is based on VLSI design of a pipelined binary tree-searched vector quantizer (VQ), utilizing space-qualifiable 1.25-micron CMOS technology. The implementation exploits VLSI system design principles such as the modularity, regular data flow, simple interconnection, localized communication, simple global control, and parallel/pipelined processing. The overall system requires 30 chips with only one VLSI processing element design. The total weight is about 1.2 lbs, with an estimated power dissipation of approximately 4 watts operating at the maximum input data rate. The projected throughput rate exceeds 5 MHz.