A Low-Power VLSI Neural Processor Design for High Speed Image Data Compression in a SOI CMOS Technology

Fang, W. C.; Lin, T. H.

NASA NTRS · 20060040840

A Low-Power VLSI Neural Processor Design for High Speed Image Data Compression in a SOI CMOS Technology

Abstract

This paper presents a low-power VLSI neural processor that has been developed for high-speed vision processing based upon the frequency-sensitive self-organization (FSO) neural algorithm.

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VLSI Neural Processor Design High Speed Image Data Compression SOI CMOS Technology

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BibTeX RIS

Fang, W. C., Lin, T. H.. 1999-01-01. A Low-Power VLSI Neural Processor Design for High Speed Image Data Compression in a SOI CMOS Technology. https://ntrs.nasa.gov/citations/20060040840

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