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Finnegan, Patrick Sean

Publications and source records attributed to Finnegan, Patrick Sean.

At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Microfabricated Ion Traps on Sapphire for Larger Trap Areas and Higher Qubit Count

Surface ion traps are a promising platform for quantum computing due to their potential to store large numbers of ions that can be addressed by electrical and optical control signals in order to implement quantum algorithms. Increasing the power of the quantum computer requires increasing the number of ions, but this poses a significant challenge in that it leads to a non-linear increase in on-chip power dissipation. The primary contributor to this power scaling in current devices is the capacitance between the radio frequency (RF) electrode and the metal plane that shields the silicon substrate from the RF signals applied to it. Silicon has traditionally been chosen for the substrate material for compatibility with the processing required for multi-metal-level traps. In this work, we address these capacitance and fabrication challenges by replacing the commonly used silicon substrate with an insulating sapphire substrate to fabricate a multi-metal-level ion trap, while still employing common semiconductor manufacturing techniques. This change in substrate allows the design to remove the metal shielding from the device design, reducing the capacitance of the RF electrode. The electrical characteristics of these traps were measured, specifically trap impedance, capacitance, and voltage breakdown, and compared to nearly identical silicon trap devices. Finally, we used laser cutting techniques to shape a sapphire wafer into bowtie shapes matching silicon traps previously fabricated at Sandia National Labs to explore solutions for integrating sapphire substrates into non-rectangular ion trap designs.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

High aspect ratio gratings fabricated by electrodeposition

A method is provided for making gratings of gold or other metal in silicon substrates. The disclosed method may achieve high aspect ratios. According to the disclosed method, a silicon wafer is through-etched. A seed layer of metal is vapor-deposited on one side of the wafer, and a layer of metal is electrodeposited on the seed layer. The electrodeposited metal plugs the trenches and provides a conductive surface for subsequent electrodeposition. The trenches are then filled by electrodeposition from within the trenches, so that the walls of the metal grating grow on the metal plugs.

Arrington, Christian Lew↗
DOE OSTI2021

Planar electrode arrays and fabrication methods thereof

The present invention relates to a method of fabricating an electrode array, in which an underlying handle wafer is removed to provide a planar device having the electrode array. Also provided are wafers including a plurality of planar devices having an electrode array, as well as sensors including such an electrode array.

Schindelholz, Eric John↗
DOE OSTI2021

Analyzing Custom Proof Masses and Quantum Limits of a Manufacturable Cavity Optical Levitation Solution

This report details results of a one-year LDRD to understand the dynamics, figures of merit, and fabrication possibilities for levitating a micro-scale, disk-shaped dielectric in an optical field. Important metrics are the stability, positional uncertainty, and required optical power to maintain levitation. Much of the results are contained in a publication written by our academic alliance collaborators. Initial structures were grown at Sandia labs and a test fabrication flow was executed. Owing to our strength in VCSEL lasers, we were particularly interested in calculations and fabrication flows that could be compatible with a VCSEL light source.

42 ENGINEERING↗