Advances in Reliability Monitoring and Failure Analysis in 3D Microsystems
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Engineering topics
Publications and source records attributed to Jordan, Matthew.
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In this study, we address the challenge of enhancing image quality and spatial resolution in computed tomography (CT) imaging by introducing simulation and fabrication of high aspect ratio, point-like transmission targets. Utilizing advanced electroplating techniques, traditionally employed in the fabrication of Through Substrate Via (TSV) interconnects for CMOS circuitry, we successfully embed copper targets within silicon substrates. This method allows us to create high-aspect-ratio features specifically designed for X-ray transmission targets, resulting in micro targets that exhibit a volume increase compared to conventional evaporated surface targets. Furthermore, we present simulation results of the X-ray spectrum generated by these targets, demonstrating their potential to significantly improve both image quality and spatial resolution in CT applications. Our findings suggest that leveraging advanced fabrication techniques can open new avenues for the development of enhanced imaging technologies in medical diagnostics and beyond.
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Surface ion traps are a promising platform for quantum computing due to their potential to store large numbers of ions that can be addressed by electrical and optical control signals in order to implement quantum algorithms. Increasing the power of the quantum computer requires increasing the number of ions, but this poses a significant challenge in that it leads to a non-linear increase in on-chip power dissipation. The primary contributor to this power scaling in current devices is the capacitance between the radio frequency (RF) electrode and the metal plane that shields the silicon substrate from the RF signals applied to it. Silicon has traditionally been chosen for the substrate material for compatibility with the processing required for multi-metal-level traps. In this work, we address these capacitance and fabrication challenges by replacing the commonly used silicon substrate with an insulating sapphire substrate to fabricate a multi-metal-level ion trap, while still employing common semiconductor manufacturing techniques. This change in substrate allows the design to remove the metal shielding from the device design, reducing the capacitance of the RF electrode. The electrical characteristics of these traps were measured, specifically trap impedance, capacitance, and voltage breakdown, and compared to nearly identical silicon trap devices. Finally, we used laser cutting techniques to shape a sapphire wafer into bowtie shapes matching silicon traps previously fabricated at Sandia National Labs to explore solutions for integrating sapphire substrates into non-rectangular ion trap designs.
Low-dimensional materials show great promise for enhanced computing and sensing performance in mission-relevant environments. However, integrating low-dimensional materials into conventional electronics remains a challenge. Here, we demonstrate a novel transfer method by which low-dimensional materials and their heterostructures can be transferred onto any arbitrary substrate. Our method relies on a water soluble GeO 2 substrate from which lowdimensional materials are transferred without significant perturbation. We apply the method to transfer a working electronic device based on a low-dimensional material. Process developments are achieved to enable the fabrication and transfer of a working electronic device, including the growth of high-k dielectric on GeO 2 by atomic layer deposition and inserting an indium diffusion barrier into the device gate stack. This work supports Sandia’s heterogeneous integration strategy to broaden the implementation of low-dimensional films and their devices.
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