Engineering topics

Kuczewski, Anthony

Publications and source records attributed to Kuczewski, Anthony.

3 records

DOE OSTI2020

Development of a High-Rate Front-End ASIC for X-Ray Spectroscopy and Diffraction Applications

We developed a new front-end application-specific integrated circuit (ASIC) to upgrade the Maia X-ray microprobe. The ASIC instruments 32 configurable channels that perform either positive or negative charge amplification, pulse shaping, peak amplitude, and time extraction along with buffered analog storage. At a gain of 3.6 V/fC, 1-μs peaking time, and a temperature of 248 K, an electronic resolution of 13 and 10 e- rms was measured with and without a silicon drift detector (SDD) sensor, respectively. A spectral resolution of 170-eV full-width at half-maximum (FWHM) at 5.9 keV was obtained with an 55Fe source. The channel linearity was better than ± 1% with rate capabilities up to 40 kcps. The ASIC was fabricated in a commercial 250-nm process with a footprint of 6.3 mm × 3.9 mm and dissipates 167 mW of static power.

Vernon, Emerson↗

DOE OSTI2019

Operational Conditions of Silicon Pixel Arrays for X-Ray Spectroscopy

Arrays of silicon sensors can be utilized in those spectroscopic applications where a high event throughput is needed, for example in synchrotron-based experiments. Yet, in such arrays several noise contributions, beyond the well-known leakage, thermal and flicker noises, can be present which are absent in single channel detectors. Additional noise is generated ultimately by the condition at the silicon/silicon oxide interface, which in turn depends on the parameters of the silicon oxide over the not-implanted gaps. We discuss how to control this region to obtain the best spectroscopic performances.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2017

Vertically Integrated Edgeless Photon Imaging Camera

The Vertically Integrated Photon Imaging Chip - Large, (VIPIC-L), is a large area, small pixel (65μm), 3D integrated, photon counting ASIC with zero-suppressed or full frame dead-time-less data readout. It features data throughput of 14.4 Gbps per chip with a full frame readout speed of 56kframes/s in the imaging mode. VIPIC-L contain 192 x 192 pixel array and the total size of the chip is 1.248cm x 1.248cm with only a 5μm periphery. It contains about 120M transistors. A 1.3M pixel camera module will be developed by arranging a 6 x 6 array of 3D VIPIC-L’s bonded to a large area silicon sensor on the analog side and to a readout board on the digital side. The readout board hosts a bank of FPGA’s, one per VIPIC-L to allow processing of up to 0.7 Tbps of raw data produced by the camera.

Fahim, Farah↗