Search NASA⌕ Search

Engineering topics

Liu, C.

Publications and source records attributed to Liu, C..

At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8*10^(-16), significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

TDC with uncontrolled delay lines: calibration approaches and precision improvement methods

The time-to-digital-converter (TDC) using uncontrolled delay lines has a simple structure and finer measurement precision since the delay cells are pure digital gates that operate at maximum speed. For every incoming hit, two “snapshots” of the delay line are taken by the register array with two strobes separated with a known time interval. With two measurements, propagation delays of each cell in the delay line can be calibrated for the operating temperature and voltage. The two measurements can also be averaged to improve the TDC measurement precision. We will discuss various calibration approaches and present test results in this work.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

A high-resolution clock phase shifter circuitry for ALTIROC

Abstract A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of 97.7 ps and an adjustable range of 25 ns. The fine delay unit is based on a Delay Locked Loop (DLL) operating at 640 MHz. The phase shifter is fabricated in a 130 nm CMOS process. The area of the phase shifter is 725 µm × 248 µm. The Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) are ±0.6 LSB and ±0.75 LSB, respectively. The jitter from −25 °C to 20 °C is less than 15.5 ps (RMS), including the contributions from the FPGA clock source and the PLL. The power consumption is 11.2 mW.

Instruments & Instrumentation↗
DOE OSTI2022

Electron-Ion Collider Design Status

The Electron-Ion Collider (EIC) is being designed for construction at Brookhaven National Laboratory. Activities have been focused on beam-beam simulations, polarization studies, and beam dynamics, as well as on maturing the layout and lattice design of the constituent accelerators and the interaction region. The latest design advances will be presented.

43 PARTICLE ACCELERATORS↗
DOE OSTI2022

OPTICS FOR STRONG HADRON COOLING IN EIC HSR-I

Insertion Region 2 (IR2) of the Relativistic Heavy Ion Collider will be modified to accommodate a Strong Hadron Cooling facility in the Hadron Storage Ring (HSR) of the Electron-Ion Collider (EIC). This paper describes the current proof-of-principle design of HSR-IR2 - layout, optical performance, design methodology, and engineering requirements. It also describes the challenges and opportunities in the future development of the HSR-IR2 design, in order to further optimize Strong Hadron Cooling performance.

Peggs, S.↗
DOE OSTI2022

QTIA, a 2.5 or 10 Gbps 4-channel array optical receiver ASIC in a 65 nm CMOS technology

Here, the Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed the lab tests with GaAs photodiodes.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

A radiation tolerant clock generator for the CMS endcap timing layer readout chip

Here, we present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear Energy Transfer (LET) from 1.3 to 62.5 MeV × cm 2 /mg.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

A 40 Gbps Optical Transceiver for Particle Physics Experiments

We present the design and the test results of a quad-channel optical transceiver module (QTRx) possibly for future particle physics experiments. The transmitters of QTRx, each at 10 Gbps, are based on a Quad-channel VCSEL Diode array Driver (QLDD) and 1 x 4 VCSEL array. The receivers of QTRx, with data rates of 2.56 Gbps or 10 Gbps per channel, are based on a Quad-channel Trans-Impedance and limiting Amplifier (QTIA) and 1 x 4 photodiode array of GaAs or InGaAs. QTRx is 20 mm x 10 mm x 5 mm and couples to an MT fiber connector. Test results indicate that QTRx achieves the design goals with a power consumption of 124 mW per transmitter channel at 10 Gbps and 120 mW at 2.56 Gbps for the receiver channel with an on-chip charge pump. The sensitivities of QTIA are -17 dBm at 2.56 Gbps and -8 dBm at 10 Gbps, respectively. Further improvements with a gold-finger interface and a more compact optical lens are being designed.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗