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Mead, Joseph

Publications and source records attributed to Mead, Joseph.

Dedicated beam position monitor pair for model-independent lattice characterization at NSLS-II

This paper reports recent lattice characterization results obtained at the National Synchrotron Light Source II (NSLS-II) storage ring, conducted without reliance on a lattice model. A pair of beam position monitors (BPMs) with bunch-by-bunch (B$\times$B) resolution, were recently installed in a section of the storage ring free of magnetic fields. The new BPM pair measured the beam, or bunch’s transverse Poincaré map precisely after the beam was excited. Linear one-turn-matrices (OTM) were then derived, and from these, the 4-dimensional coupled Twiss parameters were extracted at the locations of the BPM pair. By normalizing beam oscillation amplitudes with the Twiss parameters, the global action-variables were obtained. Additionally, these action-variables facilitated the measurement of the local Twiss parameters observed by other BPMs independent on lattice model. This method is general, and particularly useful in certain scenarios such as a round beam mode in a diffraction-limited light source ring. We applied it to assess both weakly and strongly coupled lattices at the NSLS-II ring. Through analysis of the strongly coupled lattice, the quadrupole tilt errors were estimated to be less than 400 μrad. Utilizing the BPMs’ B$\times$B resolution, for the first time we observed the variations of the linear lattice along a long bunch-train.

36 MATERIALS SCIENCE↗

Vertically Integrated Edgeless Photon Imaging Camera

The Vertically Integrated Photon Imaging Chip - Large, (VIPIC-L), is a large area, small pixel (65μm), 3D integrated, photon counting ASIC with zero-suppressed or full frame dead-time-less data readout. It features data throughput of 14.4 Gbps per chip with a full frame readout speed of 56kframes/s in the imaging mode. VIPIC-L contain 192 x 192 pixel array and the total size of the chip is 1.248cm x 1.248cm with only a 5μm periphery. It contains about 120M transistors. A 1.3M pixel camera module will be developed by arranging a 6 x 6 array of 3D VIPIC-L’s bonded to a large area silicon sensor on the analog side and to a readout board on the digital side. The readout board hosts a bank of FPGA’s, one per VIPIC-L to allow processing of up to 0.7 Tbps of raw data produced by the camera.

Fahim, Farah↗