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Perlman, M.

Publications and source records attributed to Perlman, M..

At least 19 records

Theory of Periodic-Binary-Sequence Generators

Algorithms yield feedback shift registers with maximum regularity. Report provides extensive mathematical treatment of new and previous results related to generation of pseudo-noise binary sequences by feedback shift registers. Generator architectures amenable to efficient implementation in very-large-scale integrated (VLSI) circuits. Report includes literature references to applications of such sequences in random-number generation, radar, VLSI testing, data encryption and decryption, algebraic error-detection and error-correction encoding and decoding, and feedback-shift-register synthesis of sequential machines.

Perlman, M.

Design Primer for Reed-Solomon Encoders

Design and operation of Reed-Solomon (RS) encoders discussed in document prepared as instruction manual for computer designers and others in dataprocessing field. Conventional and Berlekamp architectures compared. Engineers who equip computer memory chips with burst-error and dropout detection and correction find report especially useful.

Perlman, M.

Periodic binary sequence generators: VLSI circuits considerations

Feedback shift registers are efficient periodic binary sequence generators. Polynomials of degree r over a Galois field characteristic 2(GF(2)) characterize the behavior of shift registers with linear logic feedback. The algorithmic determination of the trinomial of lowest degree, when it exists, that contains a given irreducible polynomial over GF(2) as a factor is presented. This corresponds to embedding the behavior of an r-stage shift register with linear logic feedback into that of an n-stage shift register with a single two-input modulo 2 summer (i.e., Exclusive-OR gate) in its feedback. This leads to Very Large Scale Integrated (VLSI) circuit architecture of maximal regularity (i.e., identical cells) with intercell communications serialized to a maximal degree.

Perlman, M.

The Reed-Solomon encoders: Conventional versus Berlekamp's architecture

Concatenated coding was adopted for interplanetary space missions. Concatenated coding was employed with a convolutional inner code and a Reed-Solomon (RS) outer code for spacecraft telemetry. Conventional RS encoders are compared with those that incorporate two architectural features which approximately halve the number of multiplications of a set of fixed arguments by any RS codeword symbol. The fixed arguments and the RS symbols are taken from a nonbinary finite field. Each set of multiplications is bit-serially performed and completed during one (bit-serial) symbol shift. All firmware employed by conventional RS encoders is eliminated.

Perlman, M.

M-ary shift register

Binary devices are used to construct an m-ary linear feedback shift register.

Perlman, M.

System for generating timing and control signals

A system capable of generating every possible data frame subperiod and delayed subperiod of a data frame of length of M clock pulse intervals (CPIs) comprised of parallel modulo-m sub i counters is presented. Each m sub i is a prime power divisor of M and a cascade of alpha sub i identical modulo-p sub i counters. The modulo-p sub i counters are feedback shift registers which cycle through p sub i distinct states. Every possible nontrivial data frame subperiod and delayed subperiod is derived and a specific CPI in the data frame is detected. The number of clock pulses required to bring every modulo-p sub i counter to a respective designated state or count is determined by the Chinese remainder theorem. This corresponds to the solution of simultaneous congruences over relatively prime moduli.

Perlman, M.

Minimal hardware, binary sequence pseudonoise generator and detector

General purpose sequence generator which includes 35-stage field shift register determines mathematical properties of polynomials such as divisibility, period, order of roots, and other parameters that effect desirability of various sequences for specific applications; for example, irreducible polynomials which characterize sequences with randomness properties.

Perlman, M.

Theory and calculus of cubical complexes

Combination switching networks with multiple outputs may be represented by Boolean functions. Report has been prepared which describes derivation and use of extraction algorithm that may be adapted to simplification of such simultaneous Boolean functions.

Perlman, M.

A m-ary linear feedback shift register with binary logic

A family of m-ary linear feedback shift registers with binary logic is disclosed. Each m-ary linear feedback shift register with binary logic generates a binary representation of a nonbinary recurring sequence, producible with a m-ary linear feedback shift register without binary logic in which m is greater than 2. The state table of a m-ary linear feedback shift register without binary logic, utilizing sum modulo m feedback, is first tubulated for a given initial state. The entries in the state table are coded in binary and the binary entries are used to set the initial states of the stages of a plurality of binary shift registers. A single feedback logic unit is employed which provides a separate feedback binary digit to each binary register as a function of the states of corresponding stages of the binary registers.

Perlman, M.

An organization of a digital subsystem for generating spacecraft timing and control signals

A modulo-M counter (of clock pulses) is decomposed into parallel modulo-m sub i counters, where each m sub i is a prime power divisor of M. The modulo-p sub i counters are feedback shift registers which cycle through p sub i distinct states. By this organization, every possible nontrivial data frame subperiod and delayed subperiod may be derived. The number of clock pulses required to bring every modulo-p sub i counter to a respective designated state or count is determined by the Chinese remainder theorem. This corresponds to the solution of simultaneous congruences over relatively prime moduli.

Perlman, M.

Improved feedback shift register

Design of feedback shift register with three tap feedback decoding scheme is described. Application for obtaining sequence synchronization patterns is examined. Operation of the circuitry is described and drawings of the systems are included.

Perlman, M.

Principles of error detection and error correction codes

Report is reviewed which considers theoretical basis of groups, rings, fields, and vector spaces, and their relationship to algebraic coding theory. Report serves as summary for engineers and scientists involved in data handling and processing systems.

Perlman, M.

Theory and application of feedback shift registers

Document summarizes state-of-the-art in data processing techniques on-board spacecraft, and serves as an aid for personnel requiring tutorial knowledge of ultrareliable data processing techniques.

Perlman, M.

Digital-voltage curve generator

Curve generator capable of producing precisely repeatable curve for any single-valued function of voltage versus time uses digital approach, implemented by means of clocked feedback shift register, large scale integrated circuit diode matrix comprising about 12,000 diodes, counter, and digital-to-analog converter.

Perlman, M.