Engineering topics
Perlman, M.
Publications and source records attributed to Perlman, M..
Binary Sequence Detector-Patent
Binary sequence detector with few memory elements and minimized logic circuit complexity
Pseudonoise sequence generation with 3-tap linear feedback shift registers - Summary
Pseudonoise sequence generation with 3-tap linear feedback binary shift registers, citing reduction theorems
Pseudonoise sequence generation with three-tap linear feedback shift registers
Pseudonoise sequence generation with three-tap linear feedback shift registers
Space applications of a minimization algorithm.
Minimization algorithm for switching systems synthesis, describing design of mass spectrometer curve function generator and autonomous shift register
The synthesis of binary sequence detectors.
Synthesizing sequential network for detecting n-place nonperiodic binary sequence within data stream
A formal theory of cubical complexes Final report
Logic minimization and description of IBM 7094 program MIN6
An algorithm for the synthesis of binary sequence detectors
Algorithm for synthesis of binary sequence detectors
An algorithm for the synthesis of binary sequence detectors
Algorithm for synthesis of binary sequence detectors
Binary sequence detector uses minimum number of decision elements
Detector of an n bit binary sequence code within a serial binary data system assigns states to memory elements of a code sequence detector by employing the same order of states for the sequence detector as that of the sequence generator when the linear recursion relationship employed by the sequence generator is given.
A feedback shift-register scaler.
Scaler using ferrite-core shift register with linear-logic feedback developed for spacecraft computer clock
IMPLEMENTATION OF ERROR DETECTION AND CORRECTION USING BINARY CYCLIC CODES PART I
Error-detecting and correcting capabilities of cyclic codes