Search NASA⌕ Search

Engineering topics

Philip Neudeck

Publications and source records attributed to Philip Neudeck.

6 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2025

System for Long-Duration Electrical Testing of SiC IC Generation 12 Chips at 500 °C

The system described in this report is an improved testing rig designed to enhance measurement flexibility, provide a compact oven footprint, and reduce costs for parallel oven-testing silicon carbide (SiC) integrated circuit devices at 500 °C for long durations (greater than 100 h). The testing rig design was characterized in terms of the ovens’ internal and external temperatures, system noise, and the leakage properties of their substrate/inner boards, where the devices under test (DUTs) reside. The test rig employs a National Instruments (NI) Peripheral Component Interconnect eXtensions for Instrumentation (PXI) measurement system, room-temperature pin-switching/customizing boards, and high-temperature compact ovens.

Stephanie Booth↗
NASA NTRS2024

Mark I Silicon Carbide Integrated Circuit Test Oven Assembly and Programming Guide

This report provides a parts list, with assembly and programming instructions for building firstgeneration (Mark I) compact test ovens; this oven design is customized for prolonged functional electrical testing of prototype silicon carbide (SiC) devices at temperatures up to 500 °C (932 °F). The general approach of using multiple compact ovens to perform long-term, high-temperature electronics testing efficiently is described in a conference paper (Izadnegahdar, Alain, et al.: Alternative Setup for LongDuration Low-Duty-Cycle 600 °C Ambient Testing of SiC Integrated Circuits. International Microelectronics Assembly and Packaging Society (iMAPS) HiTECH 2021 Technology Crossover Extravaganza, 2021), available at https://ntrs.nasa.gov/citations/20210011676. The new Mark I oven design described here offers several significant improvements over the compact oven described in that paper. For example, it is constructed from commercial off-the-shelf (COTS) components and requires minimal assembly. Much of the work involves drilling holes in the two aluminum project boxes, which contain the control electronics and the oven itself. The cost of components is less than $200 (USD) per oven, which makes constructing multiple ovens affordable. In addition, the two-box design separates the high-temperature heater from the electronics, which keeps the electronics cool, prolonging the lifetime of these components.

high temperature↗
NASA NTRSDate not supplied

Early Burn-In Parasitic Conduction in 500 °C Durable SiC JFET ICs

All prior reports of long-term 500 °C operation of SiC JFET-R ICs have noted the existence of an initial “burn-in” period of changes in measured electrical characteristics for the first few hundred hours oven-testing. This work reports measurements of “burn-in parasitic MOSFET conduction” that can substantially impact the performance of some circuits during initial heat-up of JFET ICs, but then subsequently disappears after a few hours of operation at 500 °C.

silicon carbide↗
NASA NTRSDate not supplied

High Temperature Devices for Aerospace Applications

This presentation will overview important new capabilities and benefits that next-generation higher temperature electronics promise for a variety of aerospace systems and missions. Initial aerospace infusions of higher temperature electronics to be discussed include jet engines and the prolonged robotic exploration of the Venus surface. Complete redesign of systems compared to prior conventional electronics practices would yield the most revolutionary benefits. However, the inherent higher risk and expense associated with new technology adoption will likely drive a more evolutionary technology infusion process, especially since flight qualification demands large safety margins and testing that ensures reliable operation for far longer than actual mission duration. SiC pn-junction based devices are inherently capable of the most durable operation at the highest application temperatures compared other transistor technologies, but such integrated circuits (ICs) will never achieve integration levels near today’s silicon ICs. Extreme temperature high-power devices will also be de-rated compared to room-temperature performance. While the high temperature market will always be small compared to the conventional temperature mass-market, compatibility and leveraging of existing foundry manufacturing is vital to the establishment of a sustainable high temperature electronics ecosystem sufficient to significantly improve aerospace systems.

High Temperature↗
NASA NTRSDate not supplied

Progress Towards SiC ASICs for Extreme Temperature and Radiation Environments

This presentation describes development and demonstrations of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. Silicon carbide (SiC) junction field effect transistor-resistor (JFET-R) ICs fabricated by NASA Glenn Research Center with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient, 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber, and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C temperature span) without significant change in signal (input /output) or power supply voltages. While the operating frequency and functional complexity is far below silicon-based ICs, these SiC application specific ICs (ASICs) are nevertheless becoming capable of providing unique and advantageous harsh-environment circuit functionality without cooling/sheltering overhead. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards manufacture, a majority of processing steps to realize the next SiC JFET-R IC prototype wafer run have been outsourced to commercial foundry. It is expected that further upscaling combined with technology transfer to commercial production will lower investment and risk barriers to useful application deployment.

high temperature↗