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Semenov, A. [Fermilab]

Publications and source records attributed to Semenov, A. [Fermilab].

Design of Ionization Profile Monitors at the Integrable Optics Test Accelerator Facility at Fermilab

The Integrable Optics Test Accelerator (IOTA) at Fermilab is transitioning from an electron beam facility to a proton beam facility for studies in nonlinear accelerator optics and space-charge dominated proton beams. This project involves the commissioning and fabrication of Ionization Profile Monitors (IPMs) to enable beam profile measurements at IOTA. In general, IPMs work on principle of residual gas ionization by the beam to generate beam profile. This work focuses on a mechanical design that leverages a controlled injection of noble gases, primarily Argon, as the ultra-high vacuum of the IOTA ring provides insufficient residual gas for ionization. Efforts to understand vacuum integration to ensure compatibility with the storage ring environment, the integration of real-time data acquisition systems and the commissioning of the IPMs will be discussed. This project provides a versatile diagnostic tool, supporting IOTA’s role as a testbed for larger-scale accelerator facilities and contributing to the broader understanding of beam physics in high-intensity, high-space-charge regimes.

Mwaniki, M. W. [IIT, Chicago] (ORCID:0000000169057↗

Development of BPM electronics for PIP-II at Fermilab

This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA performs signal processing, time tagging, digital down-conversion, and phase drift compensation. Position and phase resolution, and thermal stability - is validated through dedicated testing.

Liu, Shengli [Fermilab] (ORCID:0009000128436936)↗

Development of BPM Electronics for PIP-II at Fermilab

This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA performs signal processing, time tagging, digital down-conversion, and phase drift compensation. Position and phase resolution, and thermal stability is validated through dedicated testing.

Liu, Shengli [Fermilab] (ORCID:0009000128436936)↗