DOE OSTI · 2997231
Development of BPM electronics for PIP-II at Fermilab
Abstract
This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA performs signal processing, time tagging, digital down-conversion, and phase drift compensation. Position and phase resolution, and thermal stability - is validated through dedicated testing.
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Liu, Shengli [Fermilab] (ORCID:0009000128436936), Eddy, Nathan [Fermilab] (ORCID:0000000291727365), Semenov, A. [Fermilab], Fellenz, Brian [Fermilab]. 2025-09-18. Development of BPM electronics for PIP-II at Fermilab. https://www.osti.gov/biblio/2997231
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