Engineering topics
Sheldon, Douglas J.
Publications and source records attributed to Sheldon, Douglas J..
Evaluating Elevated Temperature DRAM Stuck Bit Sensitivity at Room Temperature
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Assurance Technology Program Office (ATPO) Annual Report – FY2018 Office of Safety and Mission Success
UNKNOWN
Remotely Powered Reconfigurable Receiver for Extreme Sensing Platforms
Unmanned space programs are currently used to enable scientists to explore and research the furthest reaches of outer space. Systems and methods for low power communication devices in accordance with embodiments of the invention are disclosed, describing a wide variety of low power communication devices capable of remotely collecting, processing, and transmitting data from outer space in order to further mankind's goal of exploring the cosmos. Many embodiments of the invention include a Flash-based FPGA, an energy-harvesting power supply module, a sensor module, and a radio module. By utilizing technologies that withstand the harsh environment of outer space, more reliable low power communication devices can be deployed, enhancing the quality and longevity of the low power communication devices, enabling more data to be gathered and aiding in the exploration of outer space.
Screening of Supercapacitor Cells and Battery/Supercapacitor Hybrid Systems Under Thermal Vacuum Conditions
No abstract available
Systems and methods for circuit lifetime evaluation
Systems and methods for estimating the lifetime of an electrical system in accordance with embodiments of the invention are disclosed. One embodiment of the invention includes iteratively performing Worst Case Analysis (WCA) on a system design with respect to different system lifetimes using a computer to determine the lifetime at which the worst case performance of the system indicates the system will pass with zero margin or fail within a predetermined margin for error given the environment experienced by the system during its lifetime. In addition, performing WCA on a system with respect to a specific system lifetime includes identifying subcircuits within the system, performing Extreme Value Analysis (EVA) with respect to each subcircuit to determine whether the subcircuit fails EVA for the specific system lifetime, when the subcircuit passes EVA, determining that the subcircuit does not fail WCA for the specified system lifetime, when a subcircuit fails EVA performing at least one additional WCA process that provides a tighter bound on the WCA than EVA to determine whether the subcircuit fails WCA for the specified system lifetime, determining that the system passes WCA with respect to the specific system lifetime when all subcircuits pass WCA, and determining that the system fails WCA when at least one subcircuit fails WCA.
Memory Circuit Fault Simulator
Spacecraft are known to experience significant memory part-related failures and problems, both pre- and postlaunch. These memory parts include both static and dynamic memories (SRAM and DRAM). These failures manifest themselves in a variety of ways, such as pattern-sensitive failures, timingsensitive failures, etc. Because of the mission critical nature memory devices play in spacecraft architecture and operation, understanding their failure modes is vital to successful mission operation. To support this need, a generic simulation tool that can model different data patterns in conjunction with variable write and read conditions was developed. This tool is a mathematical and graphical way to embed pattern, electrical, and physical information to perform what-if analysis as part of a root cause failure analysis effort.
Programmatic Impact of SDRAM SEFI
The Elpida EDS5104(08)ABTA 512Mb SDRAM is examined for programmatic impact of SEE. Use cases for the devices including EDAC and mode register reload are examined. Results indicate some SEE mitigation methods require careful application to achieve system-level benefits, while some event types are essentially mitigated by the application use. In the studied devices MBE and SEFI are identified and investigated as mechanisms requiring special consideration.
Remotely Powered Reconfigurable Receiver for Extreme Environment Sensing Platforms
Wireless sensors connected in a local network offer revolutionary exploration capabilities, but the current solutions do not work in extreme environments of low temperatures (200K) and low to moderate radiation levels (<50 krad). These sensors (temperature, radiation, infrared, etc.) would need to operate outside the spacecraft/ lander and be totally independent of power from the spacecraft/lander. Flash memory field-programmable gate arrays (FPGAs) are being used as the main signal processing and protocol generation platform in a new receiver. Flash-based FPGAs have been shown to have at least 100 reduced standby power and 10 reduction operating power when compared to normal SRAM-based FPGA technology.
Cryogenic Quenching Process for Electronic Part Screening
The use of electronic parts at cryogenic temperatures (less than 100 C) for extreme environments is not well controlled or developed from a product quality and reliability point of view. This is in contrast to the very rigorous and well-documented procedures to qualify electronic parts for mission use in the 55 to 125 C temperature range. A similarly rigorous methodology for screening and evaluating electronic parts needs to be developed so that mission planners can expect the same level of high reliability performance for parts operated at cryogenic temperatures. A formal methodology for screening and qualifying electronic parts at cryogenic temperatures has been proposed. The methodology focuses on the base physics of failure of the devices at cryogenic temperatures. All electronic part reliability is based on the bathtub curve, high amounts of initial failures (infant mortals), a long period of normal use (random failures), and then an increasing number of failures (end of life). Unique to this is the development of custom screening procedures to eliminate early failures at cold temperatures. The ability to screen out defects will specifically impact reliability at cold temperatures. Cryogenic reliability is limited by electron trap creation in the oxide and defect sites at conductor interfaces. Non-uniform conduction processes due to process marginalities will be magnified at cryogenic temperatures. Carrier mobilities change by orders of magnitude at cryogenic temperatures, significantly enhancing the effects of electric field. Marginal contacts, impurities in oxides, and defects in conductor/conductor interfaces can all be magnified at low temperatures. The novelty is the use of an ultra-low temperature, short-duration quenching process for defect screening. The quenching process is designed to identify those defects that will precisely (and negatively) affect long-term, cryogenic part operation. This quenching process occurs at a temperature that is at least 25 C colder than the coldest expected operating temperature. This quenching process is the opposite of the standard burn-in procedure. Normal burn-in raises the temperature (and voltage) to activate quickly any possible manufacturing defects remaining in the device that were not already rejected at a functional test step. The proposed inverse burn-in or quenching process is custom-tailored to the electronic device being used. The doping profiles, materials, minimum dimensions, interfaces, and thermal expansion coefficients are all taken into account in determining the ramp rate, dwell time, and temperature.
Nanoscale Deformable Optics
Several missions and instruments in the conceptual design phase rely on the technique of interferometry to create detectable fringe patterns. The intimate emplacement of reflective material upon electron device cells based upon chalcogenide material technology permits high-speed, predictable deformation of the reflective surface to a subnanometer or finer resolution with a very high degree of accuracy. In this innovation, a layer of reflective material is deposited upon a wafer containing (perhaps in the millions) chalcogenic memory cells with the reflective material becoming the front surface of a mirror and the chalcogenic material becoming a means of selectively deforming the mirror by the application of heat to the chalcogenic material. By doing so, the mirror surface can deform anywhere from nil to nanometers in spots the size of a modern day memory cell, thereby permitting realtime tuning of mirror focus and reflectivity to mitigate aberrations caused elsewhere in the optical system. Modern foundry methods permit the design and manufacture of individual memory cells having an area of or equal to the Feature (F) size of the design (assume 65 nm). Fabrication rules and restraints generally require the instantiation of one memory cell to another no closer than 1.5 F, or, for this innovation, 90 nm from its neighbor in any direction. Chalcogenide is a semiconducting glass compound consisting of a combination of chalcogen ions, the ratios of which vary according to properties desired. It has been shown that the application of heat to cells of chalcogenic material cause a large alteration in resistance to the range of 4 orders of magnitude. It is this effect upon which chalcogenidebased commercial memories rely. Upon removal of the heat source, the chalcogenide rapidly cools and remains frozen in the excited state. It has also been shown that the chalcogenide expands in volume because of the applied heat, meaning that the coefficient of expansion of chalcogenic materials is larger than 1. In this innovation, chalcogenidebased cells are addressed (as though they are a memory), and heated and cooled according to well-established criteria. In doing so, the exact size of chalcogenide cell deformation is known and predictable; therefore, the deformation of the reflective surface is, likewise, known and predictable. Control electronics can also be implemented so that a closed-loop feedback can be maintained. Changing the contents of the chalcogenide memory cells can compensate for any change in environmental effects that might cause a change in optical path. This real-time control provides significant control and stability in use conditions.
Precise delay measurement through combinatorial logic
A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the "LUT delay chain"), also on-chip. The circuit also embeds a pulse width measurement circuit on-chip, and measures the duration of the generated pulse through the delay chain. The pulse width of the output pulse represents the delay through the delay chain without any I/O delay. The pulse width measurement circuit uses an additional asynchronous clock autonomous from the main clock and the FPGA propagation delay can be displayed on a hex display continuously for testing purposes.