Engineering topics

Sievers, M. W.

Publications and source records attributed to Sievers, M. W..

9 records

NASA NTRS1985

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.

Buehler, M. G.↗

NASA NTRS1984

Self-Checking Memory Interface

Memory-interface integrated circuit not only detects errors in data from other circuits but also detects errors within itself. Memory-interface chip encodes 16-bit words with Hamming code for single-error correction or double-error detection. Chip used in fault-tolerant computers under development by NASA.

Sievers, M. W.↗

NASA NTRS1982

Off-line, built-in test techniques for VLSI circuits

It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.

Buehler, M. G.↗

NASA NTRS1980

A general logic structure for custom LSI'S

Structure composed of standardized-circuit arrays reduces cost and complexity of fabricating special integrated circuits. Desired circuits are formed from basic mask, custom cuts, and contact points. Interactive computer program speeds design.

Sievers, M. W.↗

NASA NTRS1980

High-speed data link for moderate distances and noisy environments

A full duplex, high speed data link is described which comprises identical modules at each site for communication over coaxial cables. Each module having a digital frequency modulation (DFM) transmitter with an first-in-first-out (FIFO) data buffer for data from a digital system to be transmitted over a cable and a receiver with an FIFO data buffer for data received for a digital system at the other end of the cable. Data words are preceded by a sync word which enables the receiver. Every word transmitted, including the sync word is stored in the FIFO data buffer. This arrangement using FIFO buffers allows for asynchronous transmission of data with receipt of the data beginning with the very first bit of the sync word.

Sievers, M. W.↗

NASA NTRS1978

Noise tolerant computer link

Inexpensive computer-to-computer link facilitates data communication in electrically noisy environments. Link can connect process-control computers while reducing errors from electrical noise of manufacturing operations.

Sievers, M. W.↗

NASA NTRS1977

A high-speed computer link for moderate distances and noisy environments

To satisfy the need for a fully duplex high-speed computer data link for the antenna automation project at DSS 13, a very simple and inexpensive scheme was employed. The link requires two coaxial cables over which is sent a unipolar digital frequency modulated signal in which a logical 1 has twice the frequency of a logical 0. Optical isolators and filters reduce ground loop effects and increase noise immunity. Tests conducted in various environments and over different cable lengths at JPL, DSS 14 and DSS 13 have indicated that the link is highly effective.

Sievers, M. W.↗

NASA NTRS1977

DSS 13 automated antenna pointing subsystem phase 1 hardware

An automated antenna pointing subsystem (APS) is being installed at DSS 13 as part of the unattended station project. The function of the APS is to track an instructed position with the 26 meter antenna and to monitor the antenna servo system and meteorological conditions to ensure a proper operational environment. This article discusses the now-completed first phase of the digital hardware portion of the APS development.

Sievers, M. W.↗

NASA NTRS1976

Hardware additions to microprocessor architecture aid software development

An address trap (breakpoint) mechanism and last-in-first-out (LIFO) address stack are suggested as two additions to the basic microprocessor architecture whose functions are solely to aid the programmer. These devices provide the programmer with the ability to specify address breakpoints and to trace program execution back through N instructions, where N is the depth of the stack. Both devices, plus interface logic and buffering, have been designed for an INTEL 8080-based system using approximately 25 integrated-circuit packages.

Sievers, M. W.↗