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Thakoor, A.

Publications and source records attributed to Thakoor, A..

18 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

Transistor Level Circuit Experiments using Evolvable Hardware

The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

self configuration↗
NASA NTRS2002

Evolvable, reconfigurable hardware for future space systems

This paper overviews Evolvable Hardware (EHW) technology, examining its potential for enhancing survivability and flexibility of future space systems. EHW refers to selfconfiguration of electronic hardware by evolutionary/genetic search mechanisms. Evolvable Hardware can maintain existing functionality in the presence of faults and degradations due to aging, temperature and radiation. It can also configure itself for new functionality when required for mission changes or encountered opportunities. The paper illustrates hardware evolution in silicon using a JPL-designed programmable device reconfigurable at transistor level as the platform and a genetic algorithm running on a DSP as the reconfiguration mechanism. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The experiments demonstrate functional recovery from faults as well as from degradation at extreme temperatures indicating the possibility of expanding the operational range of extreme electronics through evolved circuit solutions.

Evolvable Hardware EHW↗
NASA NTRS2001

Evolvable Hardware for Extreme Environments: Hot or Cold

Temperature tolerant electronics and long life survivability are key capabilities required for future NASA/JPL missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. Compensation techniques, e.g., as offered by bias cancellation circuits, have also been employed. This paper presents a novel approach, based on evolvable hardware technology, which allows adaptive in situ circuit redesign/reconfiguration during the operation in the environment. This technology would complement material/device advancements and bring closer the success of missions in harsh environments. Additional information is contained in the original extended abstract.

Stoica, A.↗
NASA NTRS2000

Speed challenge: a case for hardware implementation in soft-computing

For over a decade, JPL has been actively involved in soft computing research on theory, architecture, applications, and electronics hardware. The driving force in all our research activities, in addition to the potential enabling technology promise, has been creation of a niche that imparts orders of magnitude speed advantage by implementation in parallel processing hardware with algorithms made especially suitable for hardware implementation. We review our work on neural networks, fuzzy logic, and evolvable hardware with selected application examples requiring real time response capabilities.

neural networks fuzzy logic evolvable hardware sof↗
NASA NTRS2000

On-chip learning of hyper-spectral data for real time target recognition

As the focus of our present paper, we have used the cascade error projection (CEP) learning algorithm (shown to be hardware-implementable) with on-chip learning (OCL) scheme to obtain three orders of magnitude speed-up in target recognition compared to software-based learning schemes. Thus, it is shown, real time learning as well as data processing for target recognition can be achieved.

on-chip learning Cascade Error Projection real tim↗
NASA NTRS1997

64x64 Analog Input Array for 3-Dimensional Neural Network Processor

In pattern recognition and classification for spatio-temporal problems, one of the most challenging tasks is to provide a good and valid solution in real-time. Because of time constraints, software-based neural network approaches may not be suitable for practical use. Hardware solutions seem to be good candidates for this class of problems. Currently, the Three Dimensional Analog Neural Network (3-DANN) is an effective approach to solving spatio-temporal problems in three-dimensional hardware.

spatio-temporal 3-DANN Three Dimensional Analog Ne↗
NASA NTRS1996

Radiation Behavior of Analog Neural Network Chip

A neural network experiment conducted for the Space Technology Research Vehicle (STRV-1) 1-b launched in June 1994. Identical sets of analog feed-forward neural network chips was used to study and compare the effects of space and ground radiation on the chips. Three failure mechanisms are noted.

neural networks radiation hardening graceful degra↗
NASA NTRS1995

Low Temperature Performance of High-Speed Neural Network Circuits

Artificial neural networks, derived from their biological counterparts, offer a new and enabling computing paradigm specially suitable for such tasks as image and signal processing with feature classification/object recognition, global optimization, and adaptive control. When implemented in fully parallel electronic hardware, it offers orders of magnitude speed advantage. Basic building blocks of the new architecture are the processing elements called neurons implemented as nonlinear operational amplifiers with sigmoidal transfer function, interconnected through weighted connections called synapses implemented using circuitry for weight storage and multiply functions either in an analog, digital, or hybrid scheme.

artificial neural networks image processing signal↗
NASA NTRS1995

Mine Discrimination Using Multispectral Imagery With Feedforward Neural Networks

Simulated mine detection was performed on a polarimetric hyperspectral imaging dataset collected by using an acousto-optic tunable filter camera. A feedforward artificial neural network was programmed to recognize predefined spectral "templates." The simulation results are provided along with the preprocessing steps and window sizes leading to mine detection without false alarms.

polarimetric↗