Engineering topics
Publications and source records attributed to Thakoor, Anil.
In this paper, we present a mathematical foundation, including a convergence analysis, for cascading architecture neural networks. From this, a mathematical foundation for the casade correlation learning algorithm can also be found. Furthermore, it becomes apparent that the cascade correlation scheme is a special case of an efficient hardware learning algorithm called Cascade Error Projection.
Transducers sensitive to rates of change of temperature embedded in integrated circuits and discrete electronic components damaged by overheating, according to proposal. Used to detect onset of rapid heating and to trigger shutoffs of power or other corrective actions before temperatures rise beyond safe limits. Sensors respond fast and reliably to incipient overheating because they are in direct thermal contact with vulnerable circuit elements.
Miniature capacitors containing multiple alternating thin-film dielectric and metal layers proposed, especially for use in integrated and hybrid electronic circuits. Because capacitance inversely proportional to thickness of dielectric layers, use of thin, high-quality dielectric layers affords capacitance and energy-storage densities much greater than now available. These devices much smaller and more reliable than state-of-art capacitors.
On May 11-13, 1994, JPL's Center for Space Microelectronics Technology (CSMT) hosted a neural network workshop entitled, 'A Decade of Neural Networks: Practical Applications and Prospects,' sponsored by DOD and NASA. The past ten years of renewed activity in neural network research has brought the technology to a crossroads regarding the overall scope of its future practical applicability. The purpose of the workshop was to bring together the sponsoring agencies, active researchers, and the user community to formulate a vision for the next decade of neural network research and development prospects, with emphasis on practical applications. Of the 93 participants, roughly 15% were from government agencies, 30% were from industry, 20% were from universities, and 35% were from Federally Funded Research and Development Centers (FFRDC's).
Included in this viewgraph presentation on intelligent neuroprocessors for launch vehicle health management systems (HMS) are the following: where the flight failures have been in launch vehicles; cumulative delay time; breakdown of operations hours; failure of Mars Probe; vehicle health management (VHM) cost optimizing curve; target HMS-STS auxiliary power unit location; APU monitoring and diagnosis; and integration of neural networks and fuzzy logic.
Reconfigurable and cascadable building block neural network chips, fabricated using analog VLSI design tools, are interfaced to a PC. The building block chip designs, the cascadability and the hardware-in-the-loop supervised learning aspects of these chips are described.
The JPL Center for Space Microelectronics Technology (CSMT) is actively pursuing research in the neural network theory, algorithms, and electronics as well as optoelectronic neural net hardware implementations, to explore the strengths and application potential for a variety of NASA, DoD, as well as commercial application problems, where conventional computing techniques are extremely time-consuming, cumbersome, or simply non-existent. An overview of the JPL electronic neural network hardware development activities and some of the striking applications of the JPL electronic neuroprocessors are presented.
Viewgraphs on electronic neural networks for space station are presented. Topics covered include: electronic neural networks; electronic implementations; VLSI/thin film hybrid hardware for neurocomputing; computations with analog parallel processing; features of neuroprocessors; applications of neuroprocessors; neural network hardware for terrain trafficability determination; a dedicated processor for path planning; neural network system interface; neural network for robotic control; error backpropagation algorithm for learning; resource allocation matrix; global optimization neuroprocessor; and electrically programmable read only thin-film synaptic array.
Neural network-inspired, nonvolatile, programmable associative memory using thin-film technology is demonstrated. The details of the architecture, which uses programmable resistive connection matrices in synaptic arrays and current summing and thresholding amplifiers as neurons, are described. Several synapse configurations for a high-density array of a binary connection matrix are also described. Test circuits are evaluated for operational feasibility and to demonstrate the speed of the read operation. The results are discussed to highlight the potential for a read data rate exceeding 10 megabits/sec.