Engineering topics

Thomas, J. Brooks

Publications and source records attributed to Thomas, J. Brooks.

8 records

NASA NTRS1997

Method of Implementing Digital Phase-Locked Loops

In a new formulation for digital phase-locked loops, loop-filter constants are determined from loop roots that can each be selectively placed in the s-plane on the basis of a new set of parameters, each with simple and direct physical meaning in terms of loop noise bandwidth, root-specific decay rate, and root-specific damping. Loops of first to fourth order are treated in the continuous-update approximation (B(sub L)T approaches 0) and in a discrete-update formulation with arbitrary B(sub L)T. Deficiencies of the continuous-update approximation in large-B(sub L)T applications are avoided in the new discrete-update formulation.

Stephens, Scott A.↗

NASA NTRS1995

Controlled-Root Approach To Digital Phase-Locked Loops

Performance tailored more flexibly and directly to satisfy design requirements. Controlled-root approach improved method for analysis and design of digital phase-locked loops (DPLLs). Developed rigorously from first principles for fully digital loops, making DPLL theory and design simpler and more straightforward (particularly for third- or fourth-order DPLL) and controlling performance more accurately in case of high gain.

Stephens, Scott A.↗

NASA NTRS1995

Reducing Truncation Error In Integer Processing

Improved method of rounding off (truncation of least-significant bits) in integer processing of data devised. Provides for reduction, to extremely low value, of numerical bias otherwise generated by accumulation of truncation errors from many arithmetic operations. Devised for use in integer signal processing, in which rescaling and truncation usually performed to reduce number of bits, which typically builds up in sequence of operations. Essence of method to alternate direction of roundoff (plus, then minus) on alternate occurrences of truncated values contributing to bias.

Thomas, J. Brooks↗

NASA NTRS1994

Digital GPS-Signal Processor With P-Code/No-P-Code Option

Size, power, and cost reduced by exploiting commonality. Digital signal processor for Global Positioning System (GPS) receiver set to operate in "code" mode when P code known, or in "codeless" mode when P code not known. In codeless mode, processor performs full-quadrature processing, resulting in signal-to-noise ratio (SNR) 6 dB greater than SNR's of processors not performing at full quadrature.

Thomas, J. Brooks↗

NASA NTRS1992

A Highly Digital Front End For GPS Receivers

In digital front end of GPS receiver, half-subharmonic sampling of incoming radio-frequency signal followed by summing operation produces desired baseband output in filtered and sampled form. Design generates baseband samples in guadrature with exactness in quadrature separation surpassing analog implementations. Advantages include compactness, lower cost, greater accuracy, and greater reliability.

Thomas, J. Brooks↗

NASA NTRS1991

Digital Phase-Locked Loop With Phase And Frequency Feedback

Advanced design for digital phase-lock loop (DPLL) allows loop gains higher than those used in other designs. Divided into two major components: counterrotation processor and tracking processor. Notable features include use of both phase and rate-of-change-of-phase feedback instead of frequency feedback alone, normalized sine phase extractor, improved method for extracting measured phase, and improved method for "compressing" output rate.

Thomas, J. Brooks↗

NASA NTRS1989

Counterrotator And Correlator For GPS Receivers

Accurate, all-digital, high-speed processor comprising correlator and down-converter developed for receivers in Global Positioning System (GPS). Processor reduces roundoff and commensurability errors to extremely small values. Use of digital chip and phase advancers provides outstanding control and accuracy in phase and feedback. Great flexibility imparted by provision for arbitrary starting time and integration length. Minimum-bit design requires minimum number of logical elements, thereby reducing size, power, and cost.

Thomas, J. Brooks↗

NASA NTRS1989

Chip Advancer For GPS Receiver

Instrument errors made negligible. For each integration interval, both delay and rate of change of delay initialized to small fraction of chip - for example, to order of 10 to the negative 7th power - thereby making feedback control and extraction of delay highly accurate and flexible. With appropriate selection of sampling rate relative to chip rate, commensurability errors reduced to extremely small levels. In Global Positioning System (GPS) receiver, pseudorandom code sequence generated by simple digital logic incorporating effects of time, delay, and rate of change of delay. Flexibility in starting time and sum interval very useful in aligning correlation interval with beginnings and endings of data bits.

Meehan, Thomas K.↗