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Truong, T. K.

Publications and source records attributed to Truong, T. K..

At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

A VLSI architecture for simplified arithmetic Fourier transform algorithm

The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

Reed, Irving S.↗
NASA NTRS1992

The algebraic decoding of the (41, 21, 9) quadratic residue code

A new algebraic approach for decoding the quadratic residue (QR) codes, in particular the (41, 21, 9) QR code is presented. The key ideas behind this decoding technique are a systematic application of the Sylvester resultant method to the Newton identities associated with the code syndromes to find the error-locator polynomial, and next a method for determining error locations by solving certain quadratic, cubic and quartic equations over GF(2 exp m) in a new way which uses Zech's logarithms for the arithmetic. The algorithms developed here are suitable for implementation in a programmable microprocessor or special-purpose VLSI chip. It is expected that the algebraic methods developed here can apply generally to other codes such as the BCH and Reed-Solomon codes.

Reed, Irving S.↗
NASA NTRS1992

A VLSI design for a trace-back Viterbi decoder

A systolic Viterbi decoder for convolutional codes is developed which uses the trace-back method to reduce the amount of data needed to be stored in registers. It is shown that this new algorithm requires a smaller chip size and achieves a faster decoding time than other existing methods.

Truong, T. K.↗
NASA NTRS1990

Fourier analysis and signal processing by use of the Moebius inversion formula

A novel Fourier technique for digital signal processing is developed. This approach to Fourier analysis is based on the number-theoretic method of the Moebius inversion of series. The Fourier transform method developed is shown also to yield the convolution of two signals. A computer simulation shows that this method for finding Fourier coefficients is quite suitable for digital signal processing. It competes with the classical FFT (fast Fourier transform) approach in terms of accuracy, complexity, and speed.

Reed, Irving S.↗
NASA NTRS1990

A VLSI design for a systolic Viterbi decoder

A systolic Viterbi decoder for convolutional codes is developed. This decoder uses the trace-back method to reduce the amount of data needed to be stored in registers. It is shown that this new algorithm requires a smaller chip size and achieves a faster decoding time than other existing methods.

Truong, T. K.↗
NASA NTRS1990

Simplified Correction Of Errors In Reed-Solomon Codes

New decoder realized by simplified pipeline architecture. Simplified procedure for correction of errors and erasures in Reed-Solomon codes expected to result in simpler decoding equipment. Development widens commercial applicability of Reed-Solomon codes, used to correct bursts of errors in digital communication and recording systems. Improved decoder less complex. Made more regular, simple, and suitable for implementation in both VLSI and software.

Truong, T. K.↗
NASA NTRS1989

Fast transform decoding of nonsystematic Reed-Solomon codes

A Reed-Solomon (RS) code is considered to be a special case of a redundant residue polynomial (RRP) code, and a fast transform decoding algorithm to correct both errors and erasures is presented. This decoding scheme is an improvement of the decoding algorithm for the RRP code suggested by Shiozaki and Nishida, and can be realized readily on very large scale integration chips.

Truong, T. K.↗
NASA NTRS1989

A new VLSI architecture for a single-chip-type Reed-Solomon decoder

A new very large scale integration (VLSI) architecture for implementing Reed-Solomon (RS) decoders that can correct both errors and erasures is described. This new architecture implements a Reed-Solomon decoder by using replication of a single VLSI chip. It is anticipated that this single chip type RS decoder approach will save substantial development and production costs. It is estimated that reduction in cost by a factor of four is possible with this new architecture. Furthermore, this Reed-Solomon decoder is programmable between 8 bit and 10 bit symbol sizes. Therefore, both an 8 bit Consultative Committee for Space Data Systems (CCSDS) RS decoder and a 10 bit decoder are obtained at the same time, and when concatenated with a (15,1/6) Viterbi decoder, provide an additional 2.1-dB coding gain.

Hsu, I. S.↗
NASA NTRS1989

A simplified procedure for decoding the (23,12) and (24,12) Golay codes

A simplified procedure is developed to decode the three possible erors in a (23,12) Golay codeword. A computer simulation shows that this algorithm is modular, regular and naturally suitable for both Very Large Scale Integration (VLSI) and software implementation. An extension of this new decoding procedure is used also to decode the 1/2-rate (24,12) Golay code, thereby correcting three and detecting four errors.

Truong, T. K.↗
NASA NTRS1988

A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard bases

Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to Berlekamp; the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in different areas. Finally, they are implemented on silicon chips with nitride metal oxide semiconductor technology so that the multiplier most desirable for VLSI implementation can readily be ascertained.

Hsu, I. S.↗
NASA NTRS1988

Efficient multiplication algorithms over the finite fields GF(q sup m), where q equals 3,5

Finite field multiplication is central to coding theory. For this application, there is a need for a multiplication algorithm which can be realized easily on VLSI chips. A new algorithm is developed which is based on the Babylonian multiplication technique utilizing tables of squares. This algorithm is applied to the finite fields GF(q sup m), where q equals 3 and 5. It is also shown that this multiplier can be used to compute complex multiplications defined on the direct sum of two identical copies of such Galois fields.

Truong, T. K.↗
NASA NTRS1988

A pipeline design of a fast prime factor DFT on a finite field

A conventional prime factor discrete Fourier transform (DFT) algorithm is used to realize a discrete Fourier-like transform on the finite field, GF(q sub n). This algorithm is developed to compute cyclic convolutions of complex numbers and to decode Reed-Solomon codes. Such a pipeline fast prime factor DFT algorithm over GF(q sub n) is regular, simple, expandable, and naturally suitable for VLSI implementation. An example illustrating the pipeline aspect of a 30-point transform over GF(q sub n) is presented.

Truong, T. K.↗
NASA NTRS1988

A comparison of VLSI architectures for time and transform domain decoding of Reed-Solomon codes

It is well known that the Euclidean algorithm or its equivalent, continued fractions, can be used to find the error locator polynomial needed to decode a Reed-Solomon (RS) code. It is shown that this algorithm can be used for both time and transform domain decoding by replacing its initial conditions with the Forney syndromes and the erasure locator polynomial. By this means both the errata locator polynomial and the errate evaluator polynomial can be obtained with the Euclidean algorithm. With these ideas, both time and transform domain Reed-Solomon decoders for correcting errors and erasures are simplified and compared. As a consequence, the architectures of Reed-Solomon decoders for correcting both errors and erasures can be made more modular, regular, simple, and naturally suitable for VLSI implementation.

Hsu, I. S.↗
NASA NTRS1987

A simplified procedure for correcting both errors and erasures of a Reed-Solomon code using the Euclidean algorithm

It is well known that the Euclidean algorithm or its equivalent, continued fractions, can be used to find the error locator polynomial and the error evaluator polynomial in Berlekamp's key equation needed to decode a Reed-Solomon (RS) code. A simplified procedure is developed and proved to correct erasures as well as errors by replacing the initial condition of the Euclidean algorithm by the erasure locator polynomial and the Forney syndrome polynomial. By this means, the errata locator polynomial and the errata evaluator polynomial can be obtained, simultaneously and simply, by the Euclidean algorithm only. With this improved technique the complexity of time domain RS decoders for correcting both errors and erasures is reduced substantially from previous approaches. As a consequence, decoders for correcting both errors and erasures of RS codes can be made more modular, regular, simple, and naturally suitable for both VLSI and software implementation. An example illustrating this modified decoding procedure is given for a (15, 9) RS code.

Truong, T. K.↗
NASA NTRS1987

Fast-Polynomial-Transform Program

Computer program uses fast-polynomial-transformation (FPT) algorithm applicable to two-dimensional mathematical convolutions. Two-dimensional cyclic convolutions converted to one-dimensional convolutions in polynomial rings. Program decomposes cyclic polynomials into polynomial convolutions of same length. Only FPT's and fast Fourier transforms of same length required. Modular approach saves computional resources. Program written in C.

Truong, T. K.↗
NASA NTRS1987

A comparison of VLSI architecture of finite field multipliers using dual, normal or standard basis

Three different finite field multipliers are presented: (1) a dual basis multiplier due to Berlekamp; (2) a Massy-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features which apply most suitably in different areas. Finally, they are implemented on silicon chips with nitride metal oxide semiconductor technology so that the multiplier most desirable for very large scale integration implementations can readily be ascertained.

Hsu, I. S.↗
NASA NTRS1987

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

Shyu, H. C.↗