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White, Mark

Publications and source records attributed to White, Mark.

16 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

The EGS Collab project: Outcomes and lessons learned from hydraulic fracture stimulations in crystalline rock at 1.25 and 1.5 km depth

With the goal of better understanding stimulation in crystalline rock for improving enhanced geothermal systems (EGS), the EGS Collab Project performed a series of stimulations and flow tests at 1.25 and 1.5 km depths. The tests were performed in two well-instrumented testbeds in the Sanford Underground Research Facility in Lead, South Dakota, United States. The testbed for Experiment 1 at 1.5 km depth contained two open wells for injection and production and six instrumented monitoring wells surrounding the targeted stimulation zone. Four multi-step stimulation tests targeting hydraulic fracturing and nearly year-long ambient temperature and chilled water flow tests were performed in Experiment 1. The testbed for Experiments 2 and 3 was at 1.25 km depth and contained five open wells in an outwardly fanning five-spot pattern and two fans of well-instrumented monitoring wells surrounding the targeted stimulation zone. Experiment 2 targeted shear stimulation, and Experiment 3 targeted low-flow, high-flow, and oscillating pressure stimulation strategies. Hydraulic fracturing was successful in Experiments 1 and 3 in generating a connected system wherein injected water could be collected. However, the resulting flow was distributed dynamically, and not entirely collected at the anticipated production well. Thermal breakthrough was not observed in the production well, but that could have been masked by the Joule-Thomson effect. Shear stimulation in Experiment 2 did not occur - despite attempting to pressurize the fractures most likely to shear - because of the inability to inject water into a mostly-healed fracture, and the low shear-to-normal stress ratio. The EGS Collab experiments are described to provide a background for lessons learned on topics including induced seismicity, the correlation between seismicity and permeability, distributed and dynamic flow systems, thermoelastic and pressure effects, shear stimulation, local geology, thermal breakthrough, monitoring stimulation, grouting boreholes, modeling, and system management.

15 - GEOTHERMAL ENERGY↗
NASA NTRS2017

Commercial Off-The-Shelf (COTS) Parts Risk and Reliability User and Application Guide

All COTS parts are not created equal. Because they are not created equal, the notion that one can force the commercial industry to follow a set of military specifications and standards, along with the certifications, audits and qualification commitments that go with them, is unrealistic for the sale of a few parts. The part technologies that are Defense Logistics Agency (DLA) certified or Military Specification (MS) qualified, are several generations behind the state-of-the-art high-performance parts that are required for the compact, higher performing systems for the next generation of spacecraft and instruments. The majority of the part suppliers are focused on the portion of the market that is producing high-tech commercial products and systems. To that end, in order to compete in the high performance and leading edge advanced technological systems, an alternative approach to risk assessment and reliability prediction must be considered.

White, Mark↗
NASA NTRS2012

Scaled CMOS Reliability and Considerations for Spacecraft Systems: Bottom-Up and Top-Down Perspective

New space missions will increasingly rely on more advanced technologies because of system requirements for higher performance, particularly in instruments and high-speed processing. Component-level reliability challenges with scaled CMOS in spacecraft systems from a bottom-up perspective have been presented. Fundamental Front-end and Back-end processing reliability issues with more aggressively scaled parts have been discussed. Effective thermal management from system-level to the componentlevel (top-down) is a key element in overall design of reliable systems. Thermal management in space systems must consider a wide range of issues, including thermal loading of many different components, and frequent temperature cycling of some systems. Both perspectives (top-down and bottom-up) play a large role in robust, reliable spacecraft system design.

Scaled CMOS↗
NASA NTRS2012

Scaled CMOS Reliability and Considerations for Spacecraft Systems : Bottom-Up and Top-Down Perspectives

The recently launched Mars Science Laboratory (MSL) flagship mission, named Curiosity, is the most complex rover ever built by NASA and is scheduled to touch down on the red planet in August, 2012 in Gale Crater. The rover and its instruments will have to endure the harsh environments of the surface of Mars to fulfill its main science objectives. Such complex systems require reliable microelectronic components coupled with adequate component and system-level design margins. Reliability aspects of these elements of the spacecraft system are presented from bottom- up and top-down perspectives.

derating thermal margin↗
NASA NTRS2012

Reliability Considerations for Ultra- Low Power Space Applications

NASA, the aerospace community, and other high reliability (hi-rel) users of advanced microelectronic products face many challenges as technology continues to scale into the deep sub- micron region and ULP devices are sought after. Technology trends, ULP microelectronics, scaling and performance tradeoffs, reliability considerations, and spacecraft environments will be presented from a ULP perspective for space applications.

reliability↗
NASA NTRS2012

Reliability Considerations of ULP Scaled CMOS in Spacecraft Systems

NASA, the aerospace community, and other high reliability (hi-rel) users of advanced microelectronic products face many challenges as technology continues to scale into the deep sub-micron region. Decreasing the feature size of CMOS devices not only allows more components to be placed on a single chip, but it increases performance by allowing faster switching (or clock) speeds with reduced power compared to larger scaled devices. Higher performance, and lower operating and stand-by power characteristics of Ultra-Low Power (ULP) microelectronics are not only desirable, but also necessary to meet low power consumption design goals of critical spacecraft systems. The integration of these components in such systems, however, must be balanced with the overall risk tolerance of the project.

reliability↗
NASA NTRS2011

Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

Scaled CMOS↗
NASA NTRS2010

Scaled CMOS Technology Reliability Users Guide

The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and their key parameters.

Microelectronics Reliability↗
NASA NTRS2008

Scaled CMOS technology reliability users guide

This work is sponsored by the NASA Electronic Parts and Packaging (NEPP) Program. One of the objectives of this task is to prepare a body of knowledge guideline document summarizing the CMOS technology scaling impact on CMOS parts and parts reliability for space applications. Scaling impact on parts radiation sensitivity is not addressed in this report.

Chen, Yuan↗
NASA NTRS2008

Microelectronics reliability : physics-of-failure based modeling and lifetime evaluation

This handbook presents a physics-of-failure approach to microelectronics reliability modeling and assessment. Knowledge of the root cause and physical behavior of key failure mechanisms in microelectronic devices has improved dramatically over recent years and has led to the development of more sophisticated reliability modeling tools and techniques...

White, Mark↗
NASA NTRS2006

Product Reliability Trends, Derating Considerations and Failure Mechanisms with Scaled CMOS

As microelectronics is scaled into the deep sub-micron regime, space and aerospace users of advanced technology CMOS are reassessing how scaling effects impact long-term product reliability. The effects of electromigration (EM), time-dependent-dielectric-breakdown (TDDB) and hot carrier degradation (HCI and NBTI) wearout mechanisms on scaled technologies and product reliability are investigated, accelerated stress testing across several technology nodes is performed, and FA is conducted to confirm the failure mechanism(s).

CMOS integrated circuits↗
NASA NTRS2006

Frequency Dependence of Single-Event Upset in Highly Advanced PowerPC Microprocessors

Single-event upset effects from heavy ions were measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes at three frequencies of 500, 1066 and 1600 MHz. Frequency dependence of single-event upsets is discussed. The results of our studies suggest the single-event upset in registers and D-Cache tend to increase with frequency. This might have important implications for the overall single-event upset trend as technology moves toward higher frequencies.

Cyclotron↗
NASA NTRS2005

Impact of Device Scaling on Deep Sub-micron Transistor Reliability: A Study of Reliability Trends using SRAM

As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.

CMOS integrated circuits↗
NASA NTRS2003

Impact of junction temperature on microelectronic device reliability and considerations for space applications

This paper provides a summary of an industry survey on junction temperature derating from key microelectronics suppliers, and offers recommendations to users for temperature derating for reliable operation over time. Background information on established derating factors, and reccommendations for safe operating junction temperatures for newer technologies are also presented.

device reliability↗