Engineering topics

Zamani, Nasser

Publications and source records attributed to Zamani, Nasser.

4 records

NASA NTRS1993

Predicting Lifetimes Of CMOS ASIC's From Test Data

Concise report discusses recent developments in use of semiempirical mathematical models to predict rates of failure and operating lifetimes of complementary metal oxide/semiconductor (CMOS) application-specific integrated circuits (ASIC's). Each model represents specific mechanism of failure. Once failure mechanisms and models relevant to given ASIC chosen, adjustable parameters in models fitted to life-test data acquired from representative integrated-circuit structures on test coupons fabricated along with ASIC's. Then design parameters of ASIC's incorporated into models, and models yield lifetimes.

Buehler, Martin G.↗

NASA NTRS1992

Design and qualification of the SEU/TD Radiation Monitor chip

This report describes the design, fabrication, and testing of the Single-Event Upset/Total Dose (SEU/TD) Radiation Monitor chip. The Radiation Monitor is scheduled to fly on the Mid-Course Space Experiment Satellite (MSX). The Radiation Monitor chip consists of a custom-designed 4-bit SRAM for heavy ion detection and three MOSFET's for monitoring total dose. In addition the Radiation Monitor chip was tested along with three diagnostic chips: the processor monitor and the reliability and fault chips. These chips revealed the quality of the CMOS fabrication process. The SEU/TD Radiation Monitor chip had an initial functional yield of 94.6 percent. Forty-three (43) SEU SRAM's and 14 Total Dose MOSFET's passed the hermeticity and final electrical tests and were delivered to LL.

Buehler, Martin G.↗

NASA NTRS1990

Thermal-Interaction Matrix For Resistive Test Structure

Linear mathematical model predicts increase in temperature in each segment of 15-segment resistive structure used to test electromigration. Assumption of linearity based on fact: equations that govern flow of heat are linear and coefficients in equations (heat conductivities and capacities) depend only weakly on temperature and considered constant over limited range of temperature.

Buehler, Martin G.↗

NASA NTRS1988

Temperature control in wafer-level testing of large multi-segment electromigration test structures

The paper describes two methods for maintaining a constant metallization temperature throughout a wafer-level isothermal electromigration test of large multisegment test structures where Joule-heating is high and chip to chuck thermal contact is poor. In the first method, an initial calibration of Joule heating versus metal temperature is carried out. During the isothermal electromigration test, the Joule heating is continuously monitored and the chuck temperature is adjusted based on the calibration results to maintain a constant metal temperature. In the second method, temperature sensors are fabricated on the chip and then the sensors are used to monitor the chip temperature directly. The chuck temperature is then adjusted as needed.

Zamani, Nasser↗