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Zimmerman, G.

Publications and source records attributed to Zimmerman, G..

4 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Spur-Reduced Digital Sinusoid Generation Using Higher-Order Phase Dithering

A higher-order phase dithering technique that reduces the complexity of digital sinusoid generation is presented and analyzed. M(sup th) order phase dithering denotes the addition of M independent, uniform variates to the sinusoid phase prior to word-length reduction. Spurious magnitudes due to quantization effects are accelerated from the usual -6 dBc per phase bit to -6(M + 1) dBc per phase bit, while the noise power increases linearly in M. For a given spurious specification, higher-order phase dithering permits the use of fewer phase bits than the non-dithered system, resulting in an exponential reduction in look-up table size, dramatically decreasing system complexity.

digital sinusoid generation higher-order phase dit↗
NASA NTRS1990

Large-Constraint-Length, Fast Viterbi Decoder

Scheme for efficient interconnection makes VLSI design feasible. Concept for fast Viterbi decoder provides for processing of convolutional codes of constraint length K up to 15 and rates of 1/2 to 1/6. Fully parallel (but bit-serial) architecture developed for decoder of K = 7 implemented in single dedicated VLSI circuit chip. Contains six major functional blocks. VLSI circuits perform branch metric computations, add-compare-select operations, and then store decisions in traceback memory. Traceback processor reads appropriate memory locations and puts out decoded bits. Used as building block for decoders of larger K.

Collins, O.↗
NASA NTRS1988

A long constraint length VLSI Viterbi decoder for the DSN

A Viterbi decoder, capable of decoding convolutional codes with constraint lengths up to 15, is under development for the Deep Space Network (DSN). The objective is to complete a prototype of this decoder by late 1990, and demonstrate its performance using the (15, 1/4) encoder in Galileo. The decoder is expected to provide 1 to 2 dB improvement in bit SNR, compared to the present (7, 1/2) code and existing Maximum Likelihood Convolutional Decoder (MCD). The decoder will be fully programmable for any code up to constraint length 15, and code rate 1/2 to 1/6. The decoder architecture and top-level design are described.

Statman, J. I.↗