Spur-Reduced Digital Sinusoid Generation Using Higher-Order Phase Dithering

Abstract

A higher-order phase dithering technique that reduces the complexity of digital sinusoid generation is presented and analyzed. M(sup th) order phase dithering denotes the addition of M independent, uniform variates to the sinusoid phase prior to word-length reduction. Spurious magnitudes due to quantization effects are accelerated from the usual -6 dBc per phase bit to -6(M + 1) dBc per phase bit, while the noise power increases linearly in M. For a given spurious specification, higher-order phase dithering permits the use of fewer phase bits than the non-dithered system, resulting in an exponential reduction in look-up table size, dramatically decreasing system complexity.