CRRES microelectronic test chip

Abstract

The JPL CRRES chip was designed and fabricated in 1985 and included in the CRRES MEP. MOSFET Matrix results show the effect of shielding on radiation-induced MOSFET threshold voltage shifts and channel mobility degradation. Shielded (middle board) MOSFETs have a threshold-voltage damage factor that is approximately three orders of magnitude smaller than would be estimated from Co-60 ground tests. Unshielded (outer board) MOSFETs have a threshold-voltage damage factor that would be estimated from Co-60 ground tests. Temperature swings as large as 23 C with a 22.5 orbit periodicity affected the MOSFET data and were removed from the data in order to reveal the radiation effects. This experiment demonstrated the feasibility of characterizing MOSFETs in a matrix, thus reducing the complexity and mass of the experiment.