NASA NTRS · 19940004324
VLSI chip-set for data compression using the Rice algorithm
Abstract
A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.
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Venbrux, J., Liu, N.. 1990-01-24. VLSI chip-set for data compression using the Rice algorithm. https://ntrs.nasa.gov/citations/19940004324
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