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Liu, N.

Publications and source records attributed to Liu, N..

James Webb Space Telescope Mid Infra-Red Instrument Pulse-Tube Cryocooler Electronics

The latest generation of long life, space pulse-tube cryocoolers require electronics capable of controlling self-induced vibration down to a fraction of a newton and coldhead temperature with high accuracy down to a few kelvin. Other functions include engineering diagnostics, heater and valve control, telemetry and safety protection of the cryocooler subsystem against extreme environments and operational anomalies. The electronics are designed to survive the thermal, vibration, shock and radiation environment of launch and orbit, while providing a design life in excess of 10 years on-orbit. A number of our current generation high reliability radiation-hardened electronics units are in various stages of integration on several space flight payloads. This paper describes the features and performance of our latest flight electronics designed for the pulse-tube cryocooler that is the pre-cooler for a closed cycle Joule-Thomson cooler providing 6K cooling for the James Webb Space Telescope (JWST) Mid Infra-Red Instrument (MIRI). The electronics is capable of highly accurate temperature control over the temperature range from 4K to 15K. Self-induced vibration is controlled to low levels on all harmonics up to the 16th. A unique active power filter controls peak-to-peak reflected ripple current on the primary power bus to a very low level. The 9 kg unit is capable of delivering 360W continuous power to NGAS's 3-stage pulse-tube High-Capacity Cryocooler (HCC).

thermometry

CCSDS Reed Solomon VLSI chip set

A highly efficient error correcting code has been selected by NASA as a CCSDS standard: the 16 symbol error correcting Reed Solomon code. A VLSI implementation of this decoder is described in this paper. A total of 4 full custom VLSI chips are needed that correct data in real time at an sustained rate of up to 80 Mbits/second.

Cameron, K.

Reed Solomon error correction for the space telescope

This paper reports a single 8.2mm by 8.4mm, 200,000 transistor CMOS chip implementation of the Reed Solomon code required by the Space Telescope. The chip features a 10 MHz sustained byte rate independent of error pattern. The 1.6 micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes as well as shortened codes are supported with no external buffering. Erasure corrections as well as random error corrections are supported with programmable corrections of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors.

Whitaker, S.

VLSI chip-set for data compression using the Rice algorithm

A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

Venbrux, J.