NASA NTRS · 19940004338
A programmable architecture for CMOS sequential circuits
Abstract
This paper presents a programmable architecture for sequential pass transistor circuits. The resulting circuits are such that a state machine with N states and M output is constructed using a single layout replicated N + M times.
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Whitaker, S., Maki, G., Canaris, M.. 1990-01-24. A programmable architecture for CMOS sequential circuits. https://ntrs.nasa.gov/citations/19940004338
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