NASA NTRS · 20060043109
Onboard FPGA-based SAR processing for future spaceborne systems
Abstract
We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.
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Le, Charles, Chan, Samuel, Cheng, Frank, Fang, Winston, Fischman, Mark, Hensley, Scott, Johnson, Robert, Jourdan, Michael, Marina, Miguel, Parham, Bruce, Rogez, Francois, Rosen, Paul, Shah, Biren, Taft, Stephanie. 2004-04-01. Onboard FPGA-based SAR processing for future spaceborne systems. https://ntrs.nasa.gov/citations/20060043109
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