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NASA NTRS · 20070034969

A Scalable Architecture of a Structured LDPC Decoder

Lee, Jason Kwok-San·Lee, Benjamin·Thorpe, Jeremy·Andrews, Kenneth·Dolinar, Sam·Hamkins, Jon
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Abstract

We present a scalable decoding architecture for a certain class of structured LDPC codes. The codes are designed using a small (n,r) protograph that is replicated Z times to produce a decoding graph for a (Z x n, Z x r) code. Using this architecture, we have implemented a decoder for a (4096,2048) LDPC code on a Xilinx Virtex-II 2000 FPGA, and achieved decoding speeds of 31 Mbps with 10 fixed iterations. The implemented message-passing algorithm uses an optimized 3-bit non-uniform quantizer that operates with 0.2dB implementation loss relative to a floating point decoder.

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Lee, Jason Kwok-San, Lee, Benjamin, Thorpe, Jeremy, Andrews, Kenneth, Dolinar, Sam, Hamkins, Jon. 2004-06-01. A Scalable Architecture of a Structured LDPC Decoder. https://ntrs.nasa.gov/citations/20070034969

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