PHIL Interface Design for Use With a Voltage-Regulated Amplifier: Preprint

Abstract

As inverter controls have become increasingly complex, power hardware-in-the-loop (PHIL) has emerged as a leading strategy to thoroughly assess the impact of proprietary inverter controls on a specific power system. The development of a PHIL test bed typically involves the desired inverter, a power amplifier, and a digital real-time simulator (DRTS) to control the simulated power system. As a result of PHIL nonidealities, a form of digital compensation within the DRTS is used, which is commonly referred to as a PHIL interface. The interface design for PHIL test beds has been previously examined in the literature, but many existing methods use older power amplifiers that do not contain internal voltage regulation. These existing interface methods are based around a voltage regulator within the DRTS rather than one preexisting in hardware. In this study, a three-step approach of PHIL interface development for modern power amplifiers with built-in voltage regulation is introduced and validated in hardware with a single 30-kW grid-following inverter.