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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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We will present the steps taken to derive the thermally-resilient electronics packaging design of the Mars2020 EECAM detector. We will highlight analyses and empirical test results that lead to a wide-temperature-survivable COTS component packaging design. Details of thermal cycle testing, in-process inspections, and final packaging design will be presented.
An electronic scanning pressure system that includes a plurality of pressure transducers is examined. A means obtains an electrical signal indicative of a pressure measurement from each of the plurality of pressure transducers. A multiplexing means is connected for selectivity supplying inputs from the plurality of pressure transducers to the signal obtaining means. A data bus connects the plurality of pressure transducers to the multiplexing means. A latch circuit is connected to supply control inputs to the multiplexing means. An address bus is connected to supply an address signal of a selected one of the plurality of pressure transducers to the latch circuit. In operation, each of the pressure transducers is successively scanned by the multiplexing means in response to address signals supplied on the address bus to the latch circuit.
A paper describes advanced ceramic column grid array (CCGA) packaging interconnects technology test objects that were subjected to extreme temperature thermal cycles. CCGA interconnect electronic package printed wiring boards (PWBs) of polyimide were assembled, inspected nondestructively, and, subsequently, subjected to ex - treme-temperature thermal cycling to assess reliability for future deep-space, short- and long-term, extreme-temperature missions. The test hardware consisted of two CCGA717 packages with each package divided into four daisy-chained sections, for a total of eight daisy chains to be monitored. The package is 33 33 mm with a 27 27 array of 80%/20% Pb/Sn columns on a 1.27-mm pitch. The change in resistance of the daisy-chained CCGA interconnects was measured as a function of the increasing number of thermal cycles. Several catastrophic failures were observed after 137 extreme-temperature thermal cycles, as per electrical resistance measurements, and then the tests were continued through 1,058 thermal cycles to corroborate and understand the test results. X-ray and optical inspection have been made after thermal cycling. Optical inspections were also conducted on the CCGA vs. thermal cycles. The optical inspections were conclusive; the x-ray images were not. Process qualification and assembly is required to optimize the CCGA assembly, which is very clear from the x-rays. Six daisy chains were open out of seven daisy chains, as per experimental test data reported. The daisy chains are open during the cold cycle, and then recover during the hot cycle, though some of them also opened during the hot thermal cycle..
This viewgraph information provides information on how the NASA Electronic Parts and Packaging (NEPP) Program evaluates the reliability of technologies for Electrical, Electronic, and Electromechanical (EEE) parts, and their suitability for spacecraft applications.
The 2017 Electrical and Electronics Technical Team Roadmap [1] proposes aggressive research and development targets aimed at improving power electronics technology to enable the mass-market penetration of electric-drive vehicles. Achieving these aggressive targets will require a decrease in cost (year 2025 cost target: $2.70/kW) and an increase in power density (year 2025 power density target: 100 kW/L) as compared with current on-road technology. Replacing traditional silicon device-based components with more efficient and higher-temperature wide-bandgap (WBG) semiconductor device-based components will enable increased power density. However, meeting the power density target will also require innovative thermal management solutions to increase the heat fluxes dissipated and allow for compact electronics packaging.
Higher levels of integration through the use of GaAs and silicon MMIC devices, a die-cast housing, and the reduction of the number of subassemblies has enabled a large reduction of the size and weight of the electronics package for commercial and military satellite communications. This paper presents an electronics architecture and hardware that utilizes many new integrated circuits and design techniques, and allows flexibility for future satellite frequency changes and expansion. Key features of the radio are extended C-band, InSat, Defense Satellite Communications System (DSCS), and Ku-band coverage options; 70 (or 140) MHz transponder bandwidth or L-band block bandwidth IFs; integrated RS-232 control through local handheld terminal or remote computer; remote control of crystal reference oscillator for aging and temperature compensation; integrated 2 or 5 watt solid-state power amplifiers (SSPA); optional integrated solid-state booster amplifiers to 40 watts; optional external amplifiers to 100 watts; integral beacon tracking with second integrated downcoverter for antenna positioning; radio, including low-noise block converter (LNB) and SSPA, weighs 8.5 kg and measures 32 x 23 x 16.5 cm; environmentally ruggedized for -40 to +60 C; O-ring sealed for waterproofing; passive (convection) cooling; and simple cabling and installation, with a single cable between radio and LNB, and two cables between radio and IF interface. The small size and light weight of the radio make it ideal for mounting on stabilized antenna platforms (gyroscopic or servo). Several input power options (110 or 220 VAC; +48, +12, or -24 VDC) facilitate operation on multiple platforms.
NASA Electronic Parts and Packaging (NEPP) Program Overview Mission Statement: Provide NASA's leadership for developing and maintaining guidance for the screening, qualification, test, and reliable use of EEE parts by NASA, in collaboration with other government agencies and industry. The NASA Electronic Parts Assurance Group (NEPAG) is a core portion of NEPP.
The next generation of integrated power electronics packages will implement wide-bandgap devices with ultrahigh device heat fluxes. Although jet impingement has received attention for power electronics thermal management, it is not used in commercial electric vehicles (EVs) because of the associated pressure drop and reliability concerns. Here, in this paper, we present a modular thermal management system designed for automotive power electronics. The system achieves superior thermal performance to benchmarked EVs, while adhering to reliability standards and with low pumping power. The system utilizes a low-cost and lightweight plastic manifold to generate jets over an optimized heat sink, which is embedded in the direct-bonded-copper (DBC) substrate. The embedded heat sink concept leverages additive manufacturing to add elliptical pin fins to the DBC substrate. The heat sink geometry is optimized for submerged jet impingement using a unit-cell model and an exhaustive search algorithm. The model predictions are validated using unit-cell experiments. A full-scale power module model is then used to compare the DBC-embedded heat sink against direct DBC cooling and baseplate-integrated heat sinks for single-sided (SS) and double-sided (DS) cooling concepts. Using the SS and DS DBC-embedded cooling concepts, the models predict a thermal resistance that represents a reduction of 75% and 85% compared to the 2015 BMW i3, respectively, for the same water-ethylene glycol inverter flow rate. We have shown that an inverter with a 100-kilo-Watt-per-liter power density is achievable with the proposed design.
Package manufacturers are now offering commercial-off-the-shelf column grid array (COTS CGA) packaging technologies in high-reliability versions. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronics packages. The previous reports, released in January of 2012 and January of 2013, presented package test data, assembly information, and reliability evaluation by thermal cycling for CGA packages with 1752, 1517, 1509, and 1272 inputs/outputs (I/Os) and 1-mm pitch. It presented the thermal cycling (-55C either 100C or 125C) test results for up to 200 cycles. This report presents up to 500 thermal cycles with quality assurance and failure analysis evaluation represented by optical photomicrographs, 2D real time X-ray images, dye-and-pry photomicrographs, and optical/scanning electron Microscopy (SEM) cross-sectional images. The report also presents assembly challenge using reflowing by either vapor phase or rework station of CGA and land grid array (LGA) versions of three high I/O packages both ceramic and plastic configuration. A new test vehicle was designed having high density interconnect (HDI) printed circuit board (PCB) with microvia-in-pad to accommodate both LGA packages as well as a large number of fine pitch ball grid arrays (BGAs). The LGAs either were assembled onto HDI PCB as an LGA or were solder paste print and reflow first to form solder dome on pads before assembly. Both plastic BGAs with 1156 I/O and ceramic LGAs were assembled. It also presented the X-ray inspection results as well as failures due to 200 thermal cycles. Lessons learned on assembly of ceramic LGAs are also presented.
Simultaneous interrogation of electrical signals from wide areas of the brain is vital for neuroscience research and can aid in understanding the mechanisms of brain function and treatments for neurological disorders. There emerges a demand for development of devices with highly conformal interfaces that can span large cortical regions, have sufficient spatial resolution, and chronic recording capability while keeping a small implantation footprint. In this work, we have designed 61 channel and 48 channel high-density, cortical, micro-electrocorticographic electrode arrays with 400 µm pitch on an ultra-soft but durable substrate. We have also developed a custom multiplexing integrated circuit (IC), methods for packaging the IC in a water-tight liquid crystal polymer casing, and a micro-bonding method for attaching the electronics package to the electrode array. With the integrated multiplexer, the number of external wire connections can be reduced to 16 wires, thereby diminishing the invasive footprint of the device. Both the electrode array and IC were tested in vivo in a rat model to demonstrate the ability to sense finely-localized electrophysiological signals.
Packaging technique seals electronic modules as effectively as potting in epoxy, yet permits removal of encapsulant when component change necessary. Technique encloses module in thin, rigid epoxy/fiberglass shell containing lightweight syntactic foam.
This presentation includes NASA Electronic Parts and Packaging (NEPP) Program future approaches, Radiation Hardness Assurance (RHA) examples.
Product realization is the process of defining, designing, developing, and delivering products to the market. While the main thrust of this JTEC panel was to conduct a complete investigation of the state of Japanese low-cost electronic packaging technologies, it is very difficult to totally separate the development of technology and products from the product realization process. Japan's electronics firms adhere to a product realization strategy based on a strong customer focus, a consistent commitment to excellence in design, and a cost-effective approach to technology commercialization. The Japanese product-pull strategy has been a successful driver and influencing factor in every aspect of the product development cycle.
Versatile, low cost packaging technique for spacecraft electronics
One year study program was divided into three tasks: to identify costs factors involved in packaged electronic subsystems as function of LSI density and reliability; to select most promising factors that might be modified to reduce costs in high-density packaging; and to investigate cost-saving beam tape technology for producing high-volume discrete-device packages. Results are published in 67 page report.
NASA Electronic Parts and Packaging (NEPP) Program Overview and Technology Highlights – The NEPP Program provides NASA's leadership for developing and maintaining guidance for the screening, qualification, test, and reliable use of electrical, electronic, and electromechanical parts by NASA, in collaboration with other government agencies and industry. The NASA Electronic Parts Assurance Group (NEPAG) is a core portion of NEPP. This presentation highlights key focus areas for 2019.
A closed loop system reduces pointing errors in one or more spacecraft instruments. Associated with each instrument is a electronics package (3) for commanding motion in that instrument and a pointing control system (5) for imparting motion in that instrument in response to a command (4) from the commanding package (3). Spacecraft motion compensation logic (25) compensates for instrument pointing errors caused by instrument-motion-induced spacecraft motion. Any finite number of instruments can be so compensated, by providing each pointing control system (5) and each commanding package (3), for the instruments desired to be compensated, with a link to the spacecraft motion compensation logic (25). The spacecraft motion compensation logic (25) is an electronic manifestation of the algebraic negative of a model of the dynamics of motion of the spacecraft. An example of a suitable model, and computer-simulated results, are presented.
This presentation provides a state of the art of electric-drive vehicle power electronics, and covers the APEEM Group research in thermomechanical and reliability aspects of advanced power electronics packaging. Some future directions are identified.