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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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We design a modular FPGA (field-programmable gate array) based system called QubiC to control and measure a superconducting quantum processing unit. The system includes room temperature electronics hardware, FPGA gateware, and engineering software.
the Xilinx tools relay on a component on the board (FTDI chip) to have a small memory from a particular manufacturer (Digilent) to serve as a bridge to the FPGA. What the software we're requesting to release simply does is to run between the Xilinx tools (one of them is called Vivado but there are others) and our boards so that we don't need that memory on our boards. The protocol the software uses to communicate with the Xilinx tools is called XVC (Xilinx Virtual Cable). This server code runs on the computer that is physically connected to the FPGA board, but the Xilinx tools that communicate with it can run either on that computer or some other computer connected to it over the network, this is where the network component comes into play.
SAND2025-01910O This software built in LabVIEW FPGA provides experimental control of the RF OPM prototype via a reconfigurable NI I/O card. It samples the analog input, processes it on the FPGA in real time, and generates control and feedback outputs to control and optimize the operation of the device. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.
We present an ongoing work in which a surrogate model is being developed to reproduce the response dynamics of the third-integer resonant extraction process in the Delivery Ring (DR) at Fermilab. This is in pursuit of smoothly extracting circulating beam to the Mu2e Experiment’s production target, whereby the goal is to extract a uniform slice of the circulating 1e12 protons in the DR over 25,000 turns (43 ms). The DR contains 3 harmonic sextupoles that excite a third-integer resonance and three fast, tune-ramping quadrupole magnets that drive the horizontal tune towards the 29/3 resonance. In our initial work, the surrogate model trains on a semi-analytical simulation provided in the same format as live data. Using Reinforcement Learning (and other potential ML methods), the trained surrogate acts as the “environment” in which a simple ML control agent could learn to dynamically adjust the quadrupole ramp at 430 break points within the 43 microsecond spill window. The controller will be hosted on a dedicated Arria 10 FPGA. In this work, we report the accuracy and fidelity of the surrogate model in comparison to the response dynamics of the physics simulator.
UC Davis has fabricated an ultrashort pulse reflectometer (USPR) diagnostic instrument for electron density profile measurements on compact, short duration, magnetically-confined fusion-energy concept devices such as spheromaks and FRCs. The USPR system transmits extremely short duration (~few nsec) chirped waveforms that together span 29 to 75 GHz. These chirped waveforms illuminate and reflect from the target plasma, with each frequency component reflecting from a different density layer (higher frequencies probe deeper into the plasma before reflecting). The reflected waveforms are split into roughly 42 different frequencies; time-of-flight (TOF) measurements made at each frequency with high resolution (~25 psec measurement resolution which corresponds to ~5 mm). These TOF data may then be inverted via software to generate electron density profiles with high time resolution (~10 μsec). At the heart of the system is a field programmable gate array (FPGA) based controller which collects and processes all of the USPR data in addition to generating all of the control signals required for maximum flexibility. The FPGA controller has the software flexibility to be easily reconfigured for different plasma devices, and the entire system sufficiently compact to be easily and quickly transported between devices. A high speed impulse generator was transformed into a set of three ultrashort pulse transmitter chirps using a combination of dispersive waveguide, frequency doublers and high-pass filters. A mm-wave controller was fabricated to sequentially switch between the three chirps, directing the chirps one-by-one to three different mm-wave assemblies spanning 29-75 GHz. Each mm-wave assembly consists of a high power active multiplier chain which converts the transmitter chirp to higher frequencies, and a broadband mixer which downconverts the reflected waveform to the 2-18 GHz range of the UPSR receiver. The 16-channel receiver (shared by all 3 mm-wave assemblies) was fabricated employing custom TOF modules capable of operating at a high 1 MHz sampling rate. Laboratory testing of the full system revealed the presence of unwanted harmonics from the multiplication process, with interference observed in the downconverted reflections at selected frequency channels that could not be completely filtered out. Additional interference effects arising from internal reflections within the mm-wave assemblies were minimized using a high-speed switch which served to “gate out” much of these reflections. The USPR diagnostic was transported and installed onto the HIT-SIU plasma device, becoming operational on 11/08/2022. Although designed to span 3 distinct mm-wave bands, the HIT-SIU plasmas at this time were sufficiently low density such that only the lowest of the three bands was likely to have strong plasma reflections. The system was then set to operate on only the lowest band (assembly #1), with data collected every 1 μsec rather than 3 μsec which would have been the case when cycling through all three bands. Connected to HIT-SIU, time-varying plasma reflections were observed on 9 of 16 possible frequency channels. Close examination of the data collected revealed issues previously unobserved in laboratory testing, associated with (a) reflections from the small aperture horns required for operation within the HIT-SIU device, and (b) a dependence of the recorded TOF with the threshold voltage of a given channel. Plans were made to address each of these issues before undertaking any future campaigns.
Recent advancements in use of machine learning techniques on field-programmable gate arrays (FPGAs) have allowed for implementation of embedded neural networks with extremely low latency. This is invaluable for particle detectors at the Large Hadron Collider, where latency and used area must be strictly bounded. The hls4ml framework is a procedure for converting from trained machine learning model software, to a synthesis result that can be used on an FPGA. However, running the pipeline is a time-consuming procedure, and there is a strong risk of failure. In particular, it is possible that the model is unable to be converted into a synthesis result, or that the resource consumption of the model will exceed the resources of the target FPGA. To aid with this development, we introduce wa-hls4ml, a surrogate model which uses a graph neural network to emulate the structure of the source models. The goal is to estimate the chance of success and resource consumption of an arbitrary model when passed through the hls4ml procedure, without the time consumption of actually running the pipeline.
To handle increased data flow, Jefferson Lab (JLab) is partnering with ESnet for development of an AI/ML directed compute work Load Balancer (LB) of UDP streamed data. The LB is FPGA based featuring dynamically configurable, low latency and high throughput destination address switching. The LB provides integration of edge and core computing to support JLab experimental programs, the Electron-Ion Collider, as well as data centers of the future. In the ESnet/JLab FPGA Accelerated Transport (EJFAT) initiative, the function of the LB Data Plane (DP) is to redirect data streams to selectable (but unknown to sender) destination hosts based on current worload and within that host to destination ports as a function of sub- stream id. This effects hierarchical scaling, first across compute machines for processing over a series of events and second, across ports so different data source sub-streams may be assigned to different processors for further parallelization. The LB Control Plane (CP) programs the DP using compute farm telemetry to direct and balance workloads across a compute cluster as the operating conditions require. While Proportional/Integrative/Derivative (PID) controllers are often seen in similar applications, here we investigate the feasibility of a Reinforcement Learning (RL) based schedule manager running in the CP to provide dynamic updates to the DP scheduling policy.
For acceptable implementations of technologies like wireless communications, remote monitoring, etc., strong mitigations must be developed and evaluated to ensure that new attack pathways do not increase risk for Advanced Reactors. Secure Elements can be adopted and adapted for this purpose based on tamper resistance and cryptographic abilities, but research must be done to properly integrate into critical components such as FPGA-based Important to Safety systems in conjunction with current and future regulations on cyber security features in Advanced Reactors. Typically, the integration of a Secure Element happens during the POST and UEFI boot of a computing platform, performed by the Operating System, which is not possible with FPGAs because they do not include these firmware components. Work must be done to identify a reliable and secure method for integration in FPGA-based systems which lack Operating Systems and therefore complex boot procedures, system calls, etc.
For acceptable implementations of technologies like wireless communications, remote monitoring, etc., strong mitigations must be developed and evaluated to ensure that new attack pathways do not increase risk for Advanced Reactors. Secure Elements can be adopted and adapted for this purpose based on tamper resistance and cryptographic abilities, but research must be done to properly integrate into critical components such as FPGA-based Important to Safety systems in conjunction with current and future regulations on cyber security features in Advanced Reactors. Typically, the integration of a Secure Element happens during the POST and UEFI boot of a computing platform, performed by the Operating System, which is not possible with FPGAs because they do not include these firmware components. Work must be done to identify a reliable and secure method for integration in FPGA-based systems which lack Operating Systems and therefore complex boot procedures, system calls, etc.
We report the first demonstration of using the Quantum Instrumentation and Control Kit (QICK) system on RFSoC FPGA technology to drive an entangled photon pair source and to detect the photon signals. With the QICK system, we achieve high levels of performance metrics including coincidence-to-accidental ratio exceeding 150, and entanglement visibility exceeding 95%, consistent with performance metrics achieved using conventional waveform generators. We also demonstrate simultaneous detector readout using the digitization functional of QICK, achieving internal system synchronization time resolution of 3.2 ps. The work reported in this paper represents an explicit demonstration of the feasibility for replacing commercial waveform generators and time taggers with RFSoC-FPGA technology in the operation of a quantum network, representing a cost reduction of more than an order of magnitude.
This project was motivated by State-of-the-Art (SOTA) technology that incorporates Network on Chips (NOC) for efficient data communication across the various computer kernels. For example, on the AMD Versal Field Programmable Gate Arrays (FPGA), an NoC has been incorporated for fast data communication from the programmable logic and other computer kernels (processing system, adaptable intelligence engines, etc.). The radiation effects on the legacy technology of this FPGA, such as the programmable logic, are well understood, and established methods exist to measure cross-sections when new families/generations are released; however, newly incorporated technologies, such as the NoC, are not fully understood and could introduce new failure points into the mission space.
LLRF is used to precisely control the amplitude and phase of the RF field in cavities. Often times, access to test the control algorithms with RF equipment, especially in the presence of beam, is limited or beyond reach. In such cases, testing must be done through computer modeling or simulations. Computer modeling is often too slow and difficult to interface with the LLRF hardware. Analog or digital cavity simulators are preferred as they allow for interaction with the LLRF controls platform in real-time, and compared to their analog counterparts, FPGA-based digital cavity simulators allow for a more adjustable and sophisticated implementation. The newly developed FPGA-based cavity simulator includes the cavity electrical model, the cavity mechanical model including Lorentz Force Detuning and microphonics, an amplifier model which can simulate real amplifier nonlinearities, and a beam model. The simulator has been validated using measurements from BNL’s CeC 704 MHz 5-cell SRF cryomodule.
The warm front end for the PIP-II Linac consists of an Ion-source, an RFQ, and four buncher cavities. The LLRF systems for these were the first ones developed more than a decade ago for use at the test stands. Some were VXI crate based, and others used early generation FPGA boards that are light in resources. These LLRF systems and the one for the first superconducting cryomodule, the HWR will be upgraded with the ARRIA 10 SOC-FPGA chassis with EPICS interfaces like the rest of the PIP-II Linac. The RFQ and the HWR have unique resonance control systems which are integrated into the LLRF controller hardware. The results of the initial testing with a cavity emulator will be presented.
Modern development flows that use tooling for automated building, testing, and deployment of software are becoming the norm for large scale software and hardware projects. These flows offer quite a few advantages that make them desirable, but when attempting to implement them for projects that use FPGAs, some complications can arise when attempting to integrate them with traditional FPGA toolchains and deployment workflows. In this poster, we present early our early efforts integrating the Vitis FPGA toolchain into a modern, Kuberentes and Github actions based CI/CD pipeline.
This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA performs signal processing, time tagging, digital down-conversion, and phase drift compensation. Position and phase resolution, and thermal stability is validated through dedicated testing.
The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.
Fermi National Accelerator Laboratory's CAPTAN (Compact And Programmable daTa Acquisition Node) series provides a flexible hardware platform for data acquisition across a range of experiments and facilities. The latest iteration, CAPTAN+X, is built around a Kintex-7 FPGA supporting four FPGA Mezzanine Card (FMC) connections. As part of a broader laboratory effort to bring facility systems under a Model-Based Systems Engineering (MBSE) framework, CAPTAN+X is one of several systems slated to be incorporated into this modeling environment in the near term. A necessary step toward that goal is incorporating the platform's core functionality, which centers on integration with the LXD31K4 FMC, a data converter module combining dual AD9652 analog-to-digital converters and dual AD9142A digital-to-analog converters. Achieving compatibility required resolving pin-mapping conflicts between the LXD31K4's High Pin Count connector and the CAPTAN+X's available pin types, adapting a Board Support Project originally written for an UltraScale-class evaluation board to the Kintex-7 architecture, replacing incompatible primitives, restructuring clock distribution, and manually configuring chip initialization in place of an unsupported soft-processor-based approach. Functional verification of the ADC and DAC channels, followed by closed-loop testing combining both converters with real-time filtering, confirmed correct operation of the integrated system. These results establish a working hardware and firmware baseline for the CAPTAN+X platform, positioning it for future inclusion in the laboratory's growing MBSE modeling effort.
The Fermilab Main Injector (MI) and Recycler Ring (RR) share a common beam loss monitor (BLM) system, making loss events difficult to attribute to their source machine when beam is present in both simultaneously. The Real-time Edge AI for Distributed Systems (READS) project addresses this by deblending BLM readings in real time using machine learning (ML). The current FPGA based implementation meets the sub-3 ms latency requirement but carries a resource intensive hls4ml development cycle, motivating exploration of GPU based deployment. This paper characterizes inference latency on an NVIDIA Jetson Orin Nano and introduces a packet organization scheme for assembling synchronized event frames from seven distributed BLM DAQ streams. Using a Python based DAQ simulation with injected timing jitter in place of unavailable live beam data, the pipeline achieved an average end to end latency of 0.456 ms (σ = 0.122 ms) across 167,000 test frames, comfortably meeting the timing constraint. Early outliers were attributed to TensorRT warm-up rather than steady state limitations, suggesting GPU based inference is a viable alternative to the existing FPGA implementation.