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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10

A Dynamically-Reconfigurable Burst-Mode Link Using a Nanosecond Photonic Switch

Fast optical circuit switching has great potential to solve scaling issues with traditional packet-switch based networks and improve bandwidth and power efficiency in datacenter and high-performance computing applications. One difficultly in utilizing a fast optical switch is that the optical signal must be rapidly reacquired after each switching event so as to not significantly impact the overall throughput of the system. In this work we present a system-level integration of a nanosecond-scale $2 \times 2$ silicon photonic switch with a 25-Gbps burst-mode receiver that can lock in 31 ns. A novel FPGA-based control plane was used to generate test data, control the silicon photonic switch and burst-mode receiver, and measure bit errors at 12.5 and 20 Gbps. Error-free links (BER $< 10^{-12}$ ) with system-level reconfiguration times below 60 ns (at 20 Gbps) and 90 ns (at 12.5 Gbps) including bit- and frame-synchronization are demonstrated.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

Enhancing Short-Term Flexibility through Characterization of HVDC Transmission Systems

Efficient power grid operation hinges on maintaining safety and reliability through adaptable system flexibility standards. However, in a future power grid characterized by extensive renewable energy integration, conventional system flexibility and predetermined requirements may falter under extreme conditions. This paper addresses the formidable challenge of sustaining secure and dependable power grid operations under these circumstances, emphasizing the role of controllable high voltage direct current (HVdc) transmission systems in amplifying overall system flexibility and tackling operational complexities. To quantitatively assess short-term flexibility and its associated economic benefits from HVdc within specific regions, we propose a Power Flow Distribution Factors (PTDFs) based approach. This methodology takes into account both dispatchable generators and HVdc systems, pinpointing their contributions. Through an analysis of the Western Electricity Coordinating Council (WECC) system, we demonstrate the practical application of this approach to scrutinize the impacts of existing and future HVdc lines.

Operational Flexibility, Multi-terminal HVdc, tran↗

A Hybrid Transmitter With Voltage-Mode SST Preemphasis and Current-Mode Transmitter Equalization Capable of Operating at 77 K in DUNE

The Deep Underground Neutrino Experiment (DUNE) requires that the front-end transmitters operate at cryogenic temperature and drive 25–35 m long twin-axial (twinax) cables. Here, to compensate the frequency-dependent channel loss over the long cables and alleviate the de-emphasizing of the low-frequency signal magnitude, a hybrid of a current-mode (CM) transmitter equalization (TXEQ) and a voltage-mode (VM) preemphasis is proposed. The TXEQ employs a finite-impulse response (FIR) filter to boost the high-frequency components while de-emphasizing the low-frequency signal magnitude, thereby flattening the overall channel frequency response and reducing the intersymbol interference (ISI). The VM preemphasis is proposed to further mitigate ISI by boosting the high-frequency portion without degrading the signal magnitude, allowing for high signal swing. The main driver utilizes VM source-series-terminated (SST) output stages, which offers higher signal swing and better power efficiency than the conventional CM logic (CML) drivers. To ensure the lifetime and reliability at cryogenic temperature, the transmitter is implemented in a 65-nm CMOS process operating at 1.1 V of supply voltage and employing transistors with larger than minimum lengths. Silicon measurement results at 77 K have validated the proposed approaches.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Mixed-Precision S/DGEMM Using the TF32 and TF64 Frameworks on Low-Precision AI Tensor Cores

Using NVIDIA graphics processing units (GPUs) equipped with Tensor Cores has enabled the significant acceleration of general matrix multiplication (GEMM) for applications in machine learning (ML) and artificial intelligence (AI) and in high-performance computing (HPC) generally. The use of such power-efficient, specialized accelerators can provide a performance increase between 8 × and 20 ×, albeit with a loss in precision. However, a high level of precision is required in many large scientific and HPC applications, and computing in single or double precision is still necessary for many of these applications to maintain accuracy. Fortunately, mixed-precision methods can be employed to maintain a higher level of numerical precision while also taking advantage of the performance increases from computing with lower-precision AI cores. With this in mind, we extend the state of the art by using NVIDIA’s new TF32 framework. This new framework not only burdens some constraints of the previous frameworks, such as costly 32 16-bit castings but also provides an equivalent precision and performance by using a much simpler approach. We also propose a new framework called TF64 that attempts double-precision arithmetic with low-precision Tensor Cores. Although this framework does not exist yet, we validated the correctness of this idea and achieved an equivalent of 64-bit precision on 32-bit hardware.

Valero Lara, Pedro↗

A Unidirectional Two-Compartment Neuron Circuit with On-chip STDP learning

Most neuromorphic chips implement the single-compartment point neuron model where synapse circuits connect directly to a leaky integrate and fire (LIF) soma circuit. However, when using a biologically plausible soma circuit (e.g., Hodgkin-Huxley neuron model), an interface circuitry, such as a current conveyor circuit, is needed to transmit synaptic current to the soma circuit. This is especially true for ultra-low power neuron circuits, where membrane capacitance is on the order of 20 fF. This need for an interface circuit arises because the parasitic capacitance and leakage current caused by fabrication mismatch and second-order effects of the output transistors in the synapse circuits can disturb the spiking dynamics of the soma circuit if connected without an interface. Using an interface circuit to isolate the soma’s membrane capacitor from synapses resolves this issue. We propose to use a unidirectional resistor (a transconductance circuit) to connect the synapse and soma circuits instead of conventional current conveyor circuits. Using a biologically plausible spike pattern detection model, we show that the on-chip spike-timing-dependent plasticity (STDP) learning performance of the proposed unidirectional two-compartment neuron circuit is similar to a single-compartment circuit (with a current conveyor as an interface) and additionally, it is more power-efficient and biologically plausible. The chip is fabricated in the Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm technology node and comprises a single neuron circuit.

Gautam, Ashish [ORNL]↗

Prospects and applications of on-chip lasers

Abstract Integrated silicon photonics has sparked a significant ramp-up of investment in both academia and industry as a scalable, power-efficient, and eco-friendly solution. At the heart of this platform is the light source, which in itself, has been the focus of research and development extensively. This paper sheds light and conveys our perspective on the current state-of-the-art in different aspects of application-driven on-chip silicon lasers. We tackle this from two perspectives: device-level and system-wide points of view. In the former, the different routes taken in integrating on-chip lasers are explored from different material systems to the chosen integration methodologies. Then, the discussion focus is shifted towards system-wide applications that show great prospects in incorporating photonic integrated circuits (PIC) with on-chip lasers and active devices, namely, optical communications and interconnects, optical phased array-based LiDAR, sensors for chemical and biological analysis, integrated quantum technologies, and finally, optical computing. By leveraging the myriad inherent attractive features of integrated silicon photonics, this paper aims to inspire further development in incorporating PICs with on-chip lasers in, but not limited to, these applications for substantial performance gains, green solutions, and mass production.

Zhou, Zhican↗

Chip-scale frequency combs for data communications in computing systems

Recent developments in chip-based frequency-comb technology demonstrate that comb devices can be implemented in applications where photonic integration and power efficiency are required. The large number of equally spaced comb lines that are generated make combs ideal for use in communication systems, where each line can serve as an optical carrier to allow for massively parallel wavelength-division multiplexing (WDM) transmission. In this review, we summarize the developments in integrated frequency-comb technology for use as a WDM source for communication systems in data centers and high-performance computing systems. We highlight the following three approaches for chip-scale comb generation: semiconductor modelocked lasers, electro-optic combs, and Kerr frequency combs.

Okawachi, Yoshitomo (ORCID:0000000196390549)↗

Clearing a path for light through non-Hermitian media

Abstract The performance of all active photonic devices today is greatly limited by loss. Here, we show that one can engineer a low loss path in a metal-clad lossy multi-mode waveguide while simultaneously achieving high-performance active photonic devices. We leverage non-Hermitian systems operating beyond the exceptional point to enable the redistribution of losses in a multi-mode photonic waveguide. Consequently, our multi-mode waveguide offers low propagation losses for fundamental mode while other higher order modes experience prohibitively high losses. Furthermore, we show an application of this non-Hermitian waveguide platform in designing power-efficient thermo-optic phase shifters with significantly faster response times than conventional silicon-based thermo-optic phase shifters. Our device achieves a propagation loss of less than 0.02 dB μm −1 for our non-Hermitian waveguide-based phase shifters with high performance efficiency of P π ⋅ τ = 19.1 mW μs. In addition, our phase shifters have significantly faster response time (rise/fall time), τ ≈ 1.4 μs, compared to traditional silicon based thermo-optic phase shifters.

Materials Science↗

Material aspects of giga-Hertz ZnO TFTs for wireless systems

Abstract Having enabled high-value application capabilities through mass production of flat-panel displays, X-ray imagers, and solar panels, Large-Area Electronics (LAE) holds potential to open new frontiers in wireless applications for the Internet of Things and 5G/6G, by enabling unprecedented spatial control and power efficiency through large size and flexible form factor of radiative apertures. However, this requires boosting operation frequencies from the traditional limits in the range of 10–100’s of mega-Hertz to multi giga-Hertz. In this paper, we discuss critical device metrics, to characterize zinc-oxide (ZnO) thin-film transistor (TFT) operation frequency for both active (for signal amplification) and passive components in LAE-based circuits and systems. We then describe the key structural and material approaches towards recently demonstrated LAE-based giga-Hertz wireless systems employing ZnO TFTs. Bringing LAE to the giga-Hertz regime provides a path towards flexible and meter-scale monolithic integrated wireless systems. Graphical abstract

Ma, Yue (ORCID:0000000186724090)↗

Permanent Magnets for the CEBAF 24GeV Upgrade

An upgrade of the CEBAF facility to double its present energy of 12GeV has been proposed. To provide double the number of linac passes using the existing five stacked arc beamlines, some beamlines are replaced by fixed-field accelerator (FFA) arcs, allowing multiple energies to pass through the same magnets. A solution is presented in which two of the existing electromagnetic beamlines are replaced with permanent magnet non-scaling FFA arcs, as demonstrated at CBETA. The two-stage design reduces peak magnetic field and synchrotron radiation loss compared to using a single stage. FFAs do not pulse their magnets, making permanent magnets a promising and power-efficient technology option. However, the magnetic field requirements are still at the high end of accelerator permanent magnets produced thus far (1.6T peak on beam), while the magnets must also be combined-function, having a gradient with a dipole offset. Designs using a novel oval aperture and open midplane within an adapted Halbach magnet are presented.

Brooks, S. J.↗

Fast Data Processing for Hyperspectral Sensors on Small Platforms

Hyperspectral imaging is a very promising technology for nuclear proliferation detection. However, due to size and weight restrictions, small hyperspectral platforms such as satellites and small drones lack the on-board computing resources for accurate, real-time analysis of the enormous flow of data that a continuously operating hyperspectral sensor generates. This severely limits satellite systems, which can collect far more data than what they can telemeter, and hinders the ability of all platforms to adapt their missions on the fly in response to observations. This program addresses the hyperspectral data processing challenge through development of new, fast and accurate algorithms that produce data products in real time. The algorithms circumvent the major computational bottlenecks in existing processing streams, and would be incorporated in lightweight, power-efficient single-board computer systems. The toolkit of fast algorithms will be immediately useful in current and future hyperspectral systems being built by the Government and by private industry, including drone-based systems and satellite constellations that acquire timely global imagery.

45 MILITARY TECHNOLOGY, WEAPONRY, AND NATIONAL DEF↗

Current possibilities and future opportunities for erasure coded computations

The key capability established through the research funded by this award are erasure coded computations for linear systems, in serial and in parallel. This capability enables powerful efficient and scalable alternatives to existing linear system solvers in fault-prone computational systems.

97 MATHEMATICS AND COMPUTING↗

Supporting Co-Design of Extreme-Scale Systems with In Situ Visual Analysis of Event-Driven Simulations (Final Report)

Extreme-scale systems for compute- and data-centric science are pushing the boundaries of system architectures in order to achieve ambitious goals in terms of computing capability, resilience, and power efficiency. Future systems necessitate emerging designs that incorporate new technologies, system organizations, and computer science techniques, and these changes are not yet well understood. Discrete-event-driven simulation of computing system architectures and subsystems has emerged as a productive and cost-effective means to evaluating potential designs, along with capabilities for executing these simulations of extreme-scale systems. However, techniques for analyzing the behavior of these simulations have not kept pace with our ability to perform the simulations, preventing us from extracting the most value from this promising approach. The objective of this project is to support the codesign of extreme-scale system architectures for compute and data-centric science through research and development of novel methods for analysis and visualization of large-scale event-driven simulations.

97 MATHEMATICS AND COMPUTING↗

Gallium Nitride Superjunction Fin Field Effect Transistor (Continued Funding Report)

The goal of this project is to develop the gallium vacancy assisted diffusion (GAID) method in GaN and apply it to demonstrate 2-terminal, 3-terminal, and large area Superjunction-enhanced modules. These devices will find use in high efficiency power conversion applications with the capability of operating at higher voltages, higher frequency, and less loss than comparable stat-of- the-art devices.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

High Voltage Regrown GaN P-N Diodes Enabled by Defect and Doping Control

This project studied and implemented methods to form GaN p-n diodes using selective area regrowth to achieve selective area doping. Successful selective area doping of GaN p-n diodes is an enabling factor to realize more advanced devices such as vertical transistors. The general challenge to selective area regrowth of GaN is that the primary etch method, inductively coupled plasma (ICP), damages the crystal and causes high leakage when didoes are formed by regrowth on the etched surface. Our approach used low damage etch methods following ICP etch to remove crystal damage and reduced leakage in the regrown diode. This project demonstrated 1.6 kV etched-and-regrown GaN p-n diodes using planar (non-selective) regrowth and 840 V etched-and-regrown p-n diodes using selective area regrown. Enabling factors were use of a low-damage reactive ion etch (RIE) to remove damage caused by the primary ICP etch combined with a multi-step junction terminal extension (JTE) process. Deep level defect investigation quantitatively correlated a deep level near the middle of the GaN band gap with ICP etch-induced leakage that was greatly mitigated by using a slow, low damage RIE process. This research is economically feasible for commercialization because the processes used in this project, including substrate type and source, epitaxial crystal growth and fabrication techniques are all standard to the GaN semiconductor industry. The fundamental understanding and foundational ability to produce kV-class GaN p-n diodes through etch-and-regrowth provides a path to realize high power, high efficiency GaN power switches that can significantly outperform commercial devices for next-generation electrical power conversion and transmission systems.

36 MATERIALS SCIENCE↗

Gallium Nitride Superjunction Transistor (Continued Funding Report)

The initial goal of this project is to develop the gallium vacancy assisted diffusion (GAID) method in GaN and apply it to demonstrate 2-terminal, 3-terminal, and large area Superjunction-enhanced modules. These devices will find use in high efficiency power conversion applications with the capability of operating at higher voltages, higher frequency, and less loss than comparable stat-ofthe-art devices. The approach of this project has been to utilize simulation tools to drive diffusion experiments and inform semiconductor device fabrication processes. VASP has been relied upon to simulate first principles diffusion mechanisms while SILVACO TCAD has been utilized to understand tradeoffs of the the critical dimensions in GaN devices.

42 ENGINEERING↗

Rechargeable Micro-Batteries

The quest for efficient power sources for small sensors has led to a growing interest in rechargeable micro-batteries, offering the potential to harness energy from various sources for extended periods. This project delves into a multifaceted project aimed at enhancing the performance and viability of rechargeable micro-batteries in this context. The Pacific Northwest National Laboratory (PNNL) has leveraged its expertise in primary micro-battery development, evolving into a software-driven approach for designing cylindrical micro-batteries. This project addresses the cycle life issue through innovative cell design, electrode optimization, and electrolyte refinement. A case study of the MB1842 rechargeable micro-battery demonstrates the promising outcomes of these advancements, showcasing a capacity of 0.32 mAh at ~1C (0.35 mA) and remarkable cycle performance, extending the cycle life to 510-570 cycles at 80% end-of-life (EOL), 710-760 cycles at 70% EOL and 840-940 cycles at 60% EOL, thereby ensuring a service life of 10 years for these rechargeable micro-batteries. This endeavor represents a significant stride towards unlocking the full potential of rechargeable micro-batteries, paving the way for their widespread application in small sensor technologies. The outcome from this project also successfully supports the award of a new project: 80621 - Self-Powered Modular Acoustic Telemetry System with Sensing.

25 ENERGY STORAGE↗

Celeritas R&D Report: Accelerating Geant4

Celeritas is a new Monte Carlo (MC) detector simulation code designed for computationally intensive applications on high-performance heterogeneous architectures. In the past two years Celeritas has advanced from prototyping a Graphics Processing Unit (GPU)-based single physics model in infinite medium to implementing a full set of electromagnetic (EM) physics processes in complex geometries. The current release of Celeritas, version 0.4, has incorporated full device-based navigation, an event loop in the presence of magnetic fields, and detector hit scoring. New functionality incorporates a scheduler to offload electromagnetic physics to the GPU within a Geant4-driven simulation, enabling straightforward integration of Celeritas into the high energy physics (HEP) experimental frameworks CMSSW and ATLAS FullSimLight. On the Perlmutter supercomputer, Celeritas performs EM physics between 3× and 18× faster using the machine’s Nvidia GPUs compared to using only CPUs, corresponding to an electrical power efficiency up to a factor of 5. When running a multithreaded Geant4 ATLAS test beam application with full hadronic physics, using Celeritas to accelerate the EM physics results in an overall simulation speedup of 1.7–2.2× on GPU and 1.2× on CPU. In a CMS test application using tt¯ events and the prototype Run 4 configuration, compared to Geant4 CPU, Celeritas with a Nvidia A100 improves overall throughput up to a factor of 2.7× but cannot be efficiently shared with more than 8 cores.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗