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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Standard Modular Architecture for Consumer End Plug and Play Interfaces

The growth in load and generation sources at the edge of the grid is driving the innovation in power electronic (PE) grid interfaces at the consumer end to improve the grid resiliency, reliability, security, and cost of the future infrastructure. Novel PE technologies are key enablers for the future grid infrastructure to handle the issues that arise because of the projected growth. This paper introduces a novel fundamental building block (FBB) architecture with plug-and play features. An example framework that enables co-ordination of multiple FBBs hierarchically to provide various grid functions is also presented. The FBBs are designed to be equipped with advanced features like online health monitoring, embedded intelligence, and decision-making capability for enhancing the metrics of consumer end plug and play interfaces. The paper elaborates on the proposed architecture and the developed framework i.e., the controls, communication, protection, and the corresponding timing requirements for the building blocks. The architecture and the framework have been validated through simulations and the communication framework has been validated with a control hardware in the loop platform.

Chinthavali, Madhu Sudhan↗
DOE OSTI2022

Charaterization of Emerging Computing Architectures for Dynamic Simulation of Future Power Grids with Large-Scale Power Electronics

The increasing penetration of power electronics in power grids significantly raises the computing requirements in a real-time (and/or fast) simulation of the power grid. The real-time simulation is an enabler for evaluating controllers, protection systems, new equipment, and twinning. In this paper, emerging computing architectures such as tensor processing units (TPU), neural/neuromorphic processing units (NPU), and quantum processing units (QPU) are introduced and characterized for the real-time (and/or fast) simulation of power electronics-dominated power grids. The metrics and the process to characterize emerging computing architectures to perform real-time (and/or fast) simulations of future power grids with power electronics are discussed. Three of the emerging computing units are characterized based on these metrics and the process developed. This characterization will enable identification and comparison of emerging computing architectures that can perform real-time (and/or fast) simulation of future power grids.

Choi, Jongchan↗
DOE OSTI2023

Emerging Computing Architectures: Simulation of Power Electronics in Power Grids

As the penetration of power electronics increases in power grids, new computing architectures needed to be evaluated for the simulation of high-fidelity models of power electronics in power grids in operations. In this paper, emerging computing architectures such as quantum processing units are evaluated for the simulation of power electronics in power grids. A hybrid algorithm based on classical computing and quantum computing is developed and tested for different use cases of electromagnetic transient (EMT) simulation of power electronics (PE)-based systems and simple circuits. The algorithms needed to simulate power electronics in emerging computing architectures are discussed and thereafter, simulation results are shown.

Debnath, Suman↗
DOE OSTI2023

Mixed Monopole and Bipole MTdc Architecture

Multi-terminal dc systems (MTdc) are becoming popular at transmission level voltages. High-voltage dc (HVdc) based on voltage-source-converter (VSC) technology is employed in such systems. In this paper, a new MTdc architecture, which is suitable for future expansion and easy operation under overhaul and maintenance of the converter stations is proposed. Steady state and dc fault simulation studies are performed to prove the feasibility of the MTdc architecture. Technical advantages and challenges related to the new architecture are detailed.

Jaldanki, Sreenivasa↗
DOE OSTI2021

Modeling Data Movement Performance on Heterogeneous Architectures

The cost of data movement on parallel systems varies greatly with machine architecture, job partition, and nearby jobs. Performance models that accurately capture the cost of data movement provide a tool for analysis, allowing for communication bottlenecks to be pinpointed. Modern heterogeneous architectures yield increased variance in data movement as there are a number of viable paths for inter-GPU communication. In this paper, we present performance models for the various paths of inter-node communication on modern heterogeneous architectures, including the trade-off between GPUDirect communication and copying to CPUs. Furthermore, we present a novel optimization for inter-node communication based on these models, utilizing all available CPU cores per node. Finally, we show associated performance improvements for MPI collective operations.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Neuro-Spark: A Submicrosecond Spiking Neural Networks Architecture for In-Sensor Filtering

Neuro-Spark, which is a new neuromorphic architecture with a field-programmable gate array (FPGA) implementation for ultrafast spiking neural network (SNN) inference at the edge, facilitates smart-pixel in-sensor filtering for high-energy physics experiments at the Large Hadron Collider (LHC). Utilizing the evolutionary optimization for neuromorphic systems (EONS) training method, we generate compact SNN models with 91% signal efficiency, akin to convolutional neural networks but with half the parameters. However, deploying near the detector poses a challenge because the SNN must handle a sustained input data rate exceeding 1013 GB/s. To overcome this, we propose a novel hardware architecture that uses high-level synthesis to construct a tuned architecture for the EONS-trained SNN. In addition to the analysis and validation with an AMD Xilinx Artix-A7 FPGA, our solution consumes only ç24% of FPGA LUT and flipflops. We also introduce an innovative quantization method that reduces FPGA resource utilization by ç15% without compromising accuracy. Our FPGA implementation achieves computing latency of ç10 ns for smart-pixel application inference on an edge FPGA.

Miniskar, Narasinga Rao↗
DOE OSTI2025

Microgrid Building Block Architecture, and Subcomponents Modeling and Demonstration in Controller Hardware-in-the-Loop

The recently proposed Microgrid Building Blocks (MBB) are ready-to-use components to build microgrids quickly, cheaply, and modularly. This work presents and demonstrates in controller hardware-in-the-loop (CHIL) three key subcomponents of an MBB architecture: power converter topology, control scheme, and communication framework. The addressed architecture aims for systems interconnection such as microgrid to grid and microgrid to microgrid. This paper studies each subcomponent in detail and validates the efficacy of the architecture through CHIL results.

Adib, Aswad [ORNL] (ORCID:000000020997056X)↗
DOE OSTI2024

Comparative Study of Large Language Model Architectures on Frontier

Large language models (LLMs) have garnered significant attention in both the AI community and beyond. Among these, the Generative Pre-trained Transformer (GPT) has emerged as the dominant architecture, spawning numerous variants. However, these variants have undergone pre-training under diverse conditions, including variations in input data, data preprocessing, and training methodologies, resulting in a lack of controlled comparative studies. Here we meticulously examine two prominent open-sourced GPT architectures, GPT-NeoX and LLaMA, leveraging the computational power of Frontier, the world’s first Exascale supercomputer. Employing the same materials science text corpus and a comprehensive end-to-end pipeline, we conduct a comparative analysis of their training and downstream performance. Our efforts culminate in achieving state-of-the-art performance on a challenging materials science benchmark. Furthermore, we investigate the computation and energy efficiency, and propose a computationally efficient method for architecture design. To our knowledge, these pre-trained models represent the largest available for materials science. Our findings provide practical guidance for building LLMs on HPC platforms.

Yin, Junqi↗
DOE OSTI2025

High-Intensity UV Exposure for the Rapid Screening of Silicon Photovoltaic Architectures

Advanced Si photovoltaic architectures incorporate different materials and processing pathways that influence degradation modes. Ultraviolet-induced degradation (UVID) is an understudied degradation mode for advanced cell architectures and is of increasing concern to industry due to growing adoption of UV-transparent encapsulation and bifacial technologies. In order to adopt new and evolving technologies confidently, novel component materials and processing techniques must be evaluated and designed for long-term stability, in addition to the conventional design focus on efficiency. In this work, a study protocol framework is presented for the rapid screening of unencapsulated devices against UVID. Unencapsulated passivated emitter rear contact (PERC) and tunnel oxide passivated contact (TOPCon) devices were aged under different UV irradiance intensities and measured via conventional nondestructive electrical characterization methods to assess performance degradation. Based on the results, protocol efficacy and recommendations for further study are discussed. As a result, this work is part of a broader effort to develop rapid screening processes that cut across architectures and exposure conditions to aid module manufacturers in vetting new materials choices for long-term stability.

Accelerated exposure↗
DOE OSTI2023

Novel Cascaded Ring Oscillator Vernier based TDC Architecture with a Feedthrough Reference Oscillator

Time to digital converters (TDCs) are widely used in particle physics and medical imaging to determine the relative arrival time of photons and other particles. Vernier TDCs are one of the most attractive options due to their power consumption efficiency and their small footprint. We present our newly patented innovative architecture of cascaded-stage Vernier TDCs comprised of a feedthrough reference oscillator. This architecture lead to successive Vernier measurements that result in a lower number of cycles for the same dynamic range to resolution ratio (DRRR), leading to reduced conversion time and lower jitter. To validate this architecture, a test chip was designed in 0.18~μm TSMC technology, integrating four types of cascaded Vernier TDCs with an increasing number of stages. The performance of the chip was assessed using a modular test platform specifically designed for TDCs. For comparison purposes, all TDCs were tested with a LSB of 50~ps and a dynamic range of 20~ns. The experimental results demonstrate the highest gain in performance between 1 stage Vernier and 2 stage Vernier TDCs with the precision improved from 36~ps~rms to 21~ps~rms, the maximum number of turns from 110 to 25 counts and the dead time, from 266.4~ns to 76.5~ns, on average. Adding Vernier stages is only relevant for a higher DRRR. Therefore, the 3-stage and 4-stage Vernier TDCs also show performance gains, but improvements are limited.

Scarpellini, Robin↗
DOE OSTI2024

Developments for Novel Module Architecture for Lower CapEx and Improved Recyclability for c-Si PV Modules

Photovoltaic (PV) energy production is currently increasing at a significant rate. A novel module architecture has been demonstrated that has potential for reducing manufacturing cost while improving module reliability and recycling for c-Si PV which utilizes an edge-seal. Referred to as Edge Sealed Module (ESM), this architecture eliminates the vacuum lamination process and cross-linked encapsulants on the interior of the module. Functioning prototypes of c-Si have been fabricated for stress testing in collaboration with National Renewable Energy Laboratories (NREL). These modules are being tested and compared to traditionally manufactured modules. Based on preliminary results, this module architecture is a potentially viable solution for improving the manufacturing cost and recyclability of PV modules while enhancing module performance.

costs↗
DOE OSTI2021

Optimal Control of the Energy-Saving Hybrid Hydraulic-Electric Architecture (HHEA) for Off-Highway Mobile Machines

Most off-highway constructions and agriculture equipment use hydraulics, which has unmatched power density, for power transmission and throttling as a means for control. A novel hybrid hydraulic-electric architecture (HHEA) has recently been proposed to improve efficiency for high-power machines that would have been cost-prohibitive to electrify directly. HHEA uses a set of common pressure rails (CPRs) to transmit the majority of power hydraulically and small electric motor drives to modulate that power and to achieve precise control. This article proposes a computationally efficient Lagrange multiplier method (LMM) for computing the optimal sequence of pressure rail selections to minimize energy use. This is needed to evaluate HHEA's energy-saving potential and for iterative architecture design and sizing. An interesting complication is that the cost function is not fully defined until the candidate control sequence is fully specified. This issue is dealt with by decomposing the original problem into a set of sub-problems with additional constraints that can be solved efficiently. Computational effort can be further reduced if actuators are optimized individually instead of together. However, additional steps are required to prevent the constraint functions from becoming discontinuous with respect to the Lagrange multipliers, which is necessary for meeting the constraints. Lastly, a case study of a construction machine demonstrates the efficacy of the method and shows that the HHEA reduces energy consumption by 68%-73% compared to the baseline load-sensing architecture.

Lagrange multiplier↗
DOE OSTI2020

Isochronous Architecture-Based Voltage-Active Power Droop for Multi-Inverter Systems

This article proposes an isochronous architecture for parallel inverters with only voltage-active power droop (VP-D) control for improving active power sharing as well as plug-and-play of multi-inverter-based distributed energy resources (DERs). The isochronous framework obviates the need for an explicit regulation of the frequency while allowing for sharing of reactive power. The article shows that the detrimental effects of circulating currents between inverters can be addressed in the framework developed. The isochronous architecture is implemented by employing a GPS to disseminate clock timing signals that enable the microgrid to maintain the nominal system frequency. Small signal eigenvalue analysis of a Multi-inverter Microgrid system near the steady-state operating point is presented to evaluate the system stability. Moreover, unlike traditional droop-based methods, the isochronous strategy lends itself to analytical guarantees which are developed in the article. Furthermore, the effect of delays in receiving GPS clock signals by an inverter is experimentally characterized and an inverter isolation mechanism is proposed that disconnects inverters facing large GPS communication delays. Hardware experiments on an 1.2 kVA-prototype and controller-hardware-in-the-loop validation on the CIGRE distribution network are conducted to demonstrate the effectiveness of the proposed architecture towards active and reactive power sharing between inverters with load scenarios.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2023

Extensions to the SENSEI In situ Framework for Heterogeneous Architectures

The proliferation of GPUs and accelerators in recent supercomputing systems, so called heterogeneous architectures, has led to increased complexity in execution environments and programming models as well as to deeper memory hierarchies on these systems. In this work, we discuss challenges that arise in in situ code coupling on these heterogeneous architectures. In particular, we present data and execution model extensions to the SENSEI in situ framework that are targeted at the effective use of systems with heterogeneous architectures. We then use these new data and execution model extensions to investigate several in situ placement and execution configurations and to analyze the impact these choices have on overall performance.

Loring, Burlen↗
DOE OSTI2025

QECC-Synth: A Layout Synthesizer for Quantum Error Correction Codes on Sparse Architectures

Quantum Error Correction (QEC) codes are essential for achieving fault-tolerant quantum computing (FTQC). However, their implementation faces significant challenges due to disparity between required dense qubit connectivity and sparse hardware architectures. Current approaches often either underutilize QEC circuit features or focus on manual designs tailored to specific codes and architectures, limiting their capability and generality. In response, we introduce QECC-Synth, an automated compiler for QEC code implementation that addresses these challenges. We leverage the ancilla bridge technique tailored to the requirements of QEC circuits and introduces a systematic classification of its design space flexibilities. We then formalize this problem using the MaxSAT framework to optimize these flexibilities. Evaluation shows that our method significantly outperforms existing methods while demonstrating broader applicability across diverse QEC codes and hardware architectures.

Yin, Keyi [University of California, San Diego]↗
DOE OSTI2025

Performance Impact and Trade-Offs for Tuning Key Architectural Parameters on CPU+GPU Systems

In this work, we performed an initial design space exploration of an accelerated processing unit (APU)—a hybrid CPU+GPU architecture that integrates both compute units (CUs) and memory into a unified system. This integration aims to reduce data movement, enhance memory locality, and improve energy efficiency by enabling the CPU and GPU to share memory directly. This effort focused on the interplay of key design components—cache line size, the number of CUs, and main memory technology—and the trade-offs of each configuration were analyzed. This paper highlights the various configurations’ impact on memory accesses, data reuse, and power utilization. The results provide valuable insights that can be leveraged to optimize APU architectures for high-performance and energy-efficient computing and thus create a balanced architecture. This optimization can be achieved by adopting dynamic cache management, runtime CU scaling, and advanced memory integration, highlighting the potential of APUs to address critical challenges in compute, data movement, and memory power consumption.

Asifuzzaman, Kazi [ORNL] (ORCID:0000000240044791)↗
DOE OSTI2024

EWTN: Quantifying Mass Transport to Enable Water Electrolyzer Architectures with Low Flow-Rate Sensitivity

To develop cost-effective and high-performing polymer electrolyte water electrolyzers (PEWEs) for gigawatt-scale applications, researchers have focused on reducing precious metal catalyst loadings and optimizing porous transport layers. However, the performance of PEWEs is also affected by system architecture. Mass transport losses are dependent on localized architecture and material interactions. In-situ measurements, such as current density distribution maps have demonstrated advantages in understanding the intricate characteristics and influence of two-phase flow within PEWEs. This study proposes the parameter of effective water transport number (EWTN) as a quantitative tool to investigate such current density distribution (CDD) measurements for PEWEs. Results show that higher flow-rates have EWTN values of 0.95 and above, indicating no mass transport limitations; while lower flow-rates with large gradients CDD have EWTN values between 0.6-0.8, indicating mass transport limited conditions. The new analysis also identified a correlation between mass transport losses due to bubble accumulation, membrane hydration, and ohmic overpotentials. To address these limitations, an unitized pin-type LGDL/flow-field design was developed, which effectively prevents local gas phase accumulation, resulting in improved mass transport characteristics. The results of this work show reduced flow-rate sensitivity with the pin-type architecture and ∼13% increased performance at 0.24 ml / min / cm 2 .

Electrochemistry↗
DOE OSTI2024

Perspectives on AI Architectures and Codesign for Earth System Predictability

Abstract Recently, the U.S. Department of Energy (DOE), Office of Science, Biological and Environmental Research (BER), and Advanced Scientific Computing Research (ASCR) programs organized and held the Artificial Intelligence for Earth System Predictability (AI4ESP) workshop series. From this workshop, a critical conclusion that the DOE BER and ASCR community came to is the requirement to develop a new paradigm for Earth system predictability focused on enabling artificial intelligence (AI) across the field, laboratory, modeling, and analysis activities, called model experimentation (ModEx). BER’s ModEx is an iterative approach that enables process models to generate hypotheses. The developed hypotheses inform field and laboratory efforts to collect measurement and observation data, which are subsequently used to parameterize, drive, and test model (e.g., process based) predictions. A total of 17 technical sessions were held in this AI4ESP workshop series. This paper discusses the topic of the AI Architectures and Codesign session and associated outcomes. The AI Architectures and Codesign session included two invited talks, two plenary discussion panels, and three breakout rooms that covered specific topics, including 1) DOE high-performance computing (HPC) systems, 2) cloud HPC systems, and 3) edge computing and Internet of Things (IoT). We also provide forward-looking ideas and perspectives on potential research in this codesign area that can be achieved by synergies with the other 16 session topics. These ideas include topics such as 1) reimagining codesign, 2) data acquisition to distribution, 3) heterogeneous HPC solutions for integration of AI/ML and other data analytics like uncertainty quantification with Earth system modeling and simulation, and 4) AI-enabled sensor integration into Earth system measurements and observations. Such perspectives are a distinguishing aspect of this paper. Significance Statement This study aims to provide perspectives on AI architectures and codesign approaches for Earth system predictability. Such visionary perspectives are essential because AI-enabled model-data integration has shown promise in improving predictions associated with climate change, perturbations, and extreme events. Our forward-looking ideas guide what is next in codesign to enhance Earth system models, observations, and theory using state-of-the-art and futuristic computational infrastructure.

54 ENVIRONMENTAL SCIENCES↗