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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

Use of SX Series Devices and IEEE 1149.1 JTAG Circuitry

This report summarizes the use of SX series devices and their JTAG 1149.1 circuitry. 'JTAG' circuitry was originally designed to standardize testing of boards via a simple control port interface electrically without having to use devices such as a bed of nails tester. JTAG is also used for other functions such as executing built-in-test sequences, identifying devices, or, through custom instructions, other functions designed in by the chip designer. The JTAG circuitry is designed for test only; it has no functional use in the integrated circuit during normal operations. The JTAG circuitry and the mode of the device is controlled by a circuit block known as the 'TAP controller,' which is a sixteen-state state machine along with various registers. The controller is normally in an operational state known as TEST-LOGIC-RESET. In this state, the device is held in a fully functional, operating mode. However, a Single Event Upset (SEU) may remove the TAP controller from this state, causing a loss of control of the integrated circuit, unless certain precautions are taken, such as grounding the optional JTAG TRST signal.

Katz, Richard B.↗
NASA NTRS1998

Use of SX Series Devices and IEEE 1149.1 JTAG Circuitry

This report summarizes the use of SX series devices and their JTAG 1149.1 circuitry. 'JTAG' circuitry was originally designed to standardize testing of boards via a simple control port interface electrically without having to use devices such as a bed of nails tester. JTAG is also used for other functions such as executing built-in-test sequences, identifying devices, or, through custom instructions, other functions designed in by the chip designer. The JTAG circuitry is designed for test only; it has no functional use in the integrated circuit during normal operations. The JTAG circuitry and the mode of the device is controlled by a circuit block known as the 'TAP controller,' which is a sixteen-state state machine along with various registers. The controller is normally in an operational state known as TEST-LOGIC-RESET. In this state, the device is held in a fully functional, operational mode. However, a Single Event Upset (SEU) may remove the TAP controller from this state, causing a loss of control of the integrated circuit, unless certain precautions are taken, such as grounding the optional JTAG TRST signal.

Katz, Richard B.↗
NASA NTRS1994

JTEC Panel report on microelectromechanical systems in Japan

This report summarizes recent activities in the development of microelectromechanical systems (MEMS) in Japan. For the purposes of this study, 'MEMS' means batch-fabricated miniature devices that convert physical parameters to or from electrical signals and that depend on mechanical structures or parameters in important ways for their operation. The report covers advanced materials and process technology; sensors and sensing microstructures; microactuators and actuation mechanisms; sensor-circuit integration and system partitioning; advanced packaging, microassembly, and testing technologies; and MEMS design techniques, applications, and infrastructure. The panel found that Japanese industry is emphasizing approaches to MEMS that are similar to those taken by U.S. industry (i.e., approaches based on silicon integrated-circuit technology); these efforts are comparable in their level of development to those in the United States. However, the ten-year, $250 million, MITI-sponsored program in micromachines emphasizes the miniaturization of more traditional (nonlithographic) machining processes, an area in which there is no comparable U.S. effort. Packaging technology and applications for batch-fabricated MEMS devices is considered a major challenge in both countries. The panel concluded that these and other issues will require global leadership and international cooperation to realize the benefits of MEMS in a timely way.

Wise, Kensall D.↗
NASA NTRS1975

Failure analysis of electronic parts: Laboratory methods

Failure analysis test methods are presented for use in analyzing candidate electronic parts and in improving future design reliability. Each test is classified as nondestructive, semidestructive, or destructive. The effects upon applicable part types (i.e. integrated circuit, transitor) are discussed. Methodology is given for performing the following: immersion tests, radio graphic tests, dewpoint tests, gas ambient analysis, cross sectioning, and ultraviolet examination.

Anstead, R. J.↗
NASA NTRS2006

Single Event Effects Test Results for Advanced Field Programmable Gate Arrays

Reconfigurable Field Programmable Gate Arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turnApplication Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm2/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm2/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm2/mg and a high LET cross section of about lxlO-6 cm2/bit for storing ones and about lxl0-7 cm2/bit for storing zeros . Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.

Field Programmable Gate Arrays↗
NASA NTRS1968

Small, low power analog-to-digital converter

A small, low-power, high-speed, 8-bit analog-to-digital converter using silicon chip integrated circuits is suitable for use in airborne test data systems. The successive approximation method of analog-to-digital conversion is used to generate the digital output.

Dunn, R. D.↗
NASA NTRS1991

Analog VLSI neural network integrated circuits

Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

Kub, F. J.↗
NASA NTRS2018

Yearlong 500 °C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, upscaling, and testing of 500°C durable two-level interconnect 4H-SiC JFET IC technology undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for 1 year (8760 hours) at 500°C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016.

Neudeck, Philip G.↗
NASA NTRS2000

A Boundary Scan Test Vehicle for Direct Chip Attach Testing

To facilitate the new faster, better and cheaper spacecraft designs, smaller more mass efficient avionics and instruments are using higher density electronic packaging technologies such as direct chip attach (DCA). For space flight applications, these technologies need to have demonstrated reliability and reasonably well defined fabrication and assembly processes before they will be accepted as baseline designs in new missions. As electronics shrink in size, not only can repair be more difficult, but 49 probing" circuitry can be very risky and it becomes increasingly more difficult to identify the specific source of a problem. To test and monitor these new technologies, the Direct Chip Attach Task, under NASA's Electronic Parts and Packaging Program (NEPP), chose the test methodology of boundary scan testing. The boundary scan methodology was developed for interconnect integrity and functional testing at hard to access electrical nodes. With boundary scan testing, active devices are used and failures can be identified to the specific device and lead. This technology permits the incorporation of "built in test" into almost any circuit and thus gives detailed test access to the highly integrated electronic assemblies. This presentation will describe boundary scan, discuss the development of the boundary scan test vehicle for DCA and current plans for testing of direct chip attach configurations.

Parsons, Heather A.↗
NASA NTRS1996

Compiled Data On Single-Event Effects Caused By Heavy Ions

Report presents test data on susceptibility of new set of digital integrated circuits and other semiconductor products to single-event effects (soft errors and latchups) caused by heavy ions incident at high energies. Data used to develop generalizations for protecting electronic equipment from single-event effects. In some cases, tested parts selected as candidates for use in specific applications.

Nichols, Donald K.↗
NASA NTRS2008

Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500 C

The fabrication and testing of the first semiconductor transistors and small-scale integrated circuits (ICs) to achieve up to 3000 h of stable electrical operation at 500 C in air ambient is reported. These devices are based on an epitaxial 6H-SiC junction field-effect transistor process that successfully integrated high temperature ohmic contacts, dielectric passivation, and ceramic packaging. Important device and circuit parameters exhibited less than 10% of change over the course of the 500 C operational testing. These results establish a new technology foundation for realizing durable 500 C ICs for combustion-engine sensing and control, deep-well drilling, and other harsh-environment applications.

Neudeck, Philip G.↗
NASA NTRS2018

Engineering Trade-off Considerations Regarding Design-for-Security, Design-for-Verification, and Design-for-Test

The United States government has identified that application specific integrated circuit (ASIC) and field programmable gate array (FPGA) hardware are at risk from a variety of adversary attacks. This finding affects system security and trust. Consequently, processes are being developed for system mitigation and countermeasure application. The scope of this tutorial pertains to potential vulnerabilities and countermeasures within the ASIC/FPGA design cycle. The presentation demonstrates how design practices can affect the risk for the adversary to: change circuitry, steal intellectual property, and listen to data operations. An important portion of the design cycle is assuring the design is working as specified or as expected. This is accomplished by exhaustive testing of the target design. Alternatively, it has been shown that well established schemes for test coverage enhancement (design-for-verification (DFV) and design-for-test (DFT)) can create conduits for adversary accessibility. As a result, it is essential to perform a trade between robust test coverage versus reliable design implementation. The goal of this tutorial is to explain the evolution of design practices; review adversary accessibility points due to DFV and DFT circuitry insertion (back door circuitry); and to describe common engineering trade-off considerations for test versus adversary threats.

Design for reliability (DFR)↗
NASA NTRS1976

Irradiate-anneal screening of total dose effects in semiconductor devices

An extensive investigation of irradiate-anneal (IRAN) screening against total dose radiation effects was carried out as part of a program to harden the Mariner Jupiter/Saturn 1977 (MJS'77) spacecraft to survive the Jupiter radiation belts. The method consists of irradiating semiconductor devices with Cobalt-60 to a suitable total dose under representative bias conditions and of separating the parts in the undesired tail of the distribution from the bulk of the parts by means of a predetermined acceptance limit. The acceptable devices are then restored close to their preirradiation condition by annealing them at an elevated temperature. IRAN was used when lot screen methods were impracticable due to lack of time, and when members of a lot showed a diversity of radiation response. The feasibility of the technique was determined by testing of a number of types of linear bipolar integrated circuits, analog switches, n-channel JFETS and bipolar transistors. Based on the results of these experiments a number of device types were selected for IRAN of flight parts in the MJS'77 spacecraft systems. The part types, screening doses, acceptance criteria, number of parts tested and rejected as well as the program steps are detailed.

Stanley, A. G.↗
NASA NTRS1990

NASA Langley and AF RADC high-speed fiber optic transceiver program

NASA-Langley and the USAF Rome Air Development Center have been pursuing the development of military- and space-qualified fiber optic transceivers for a variety of ground-based, space-based, and general avionic applications. An initial development pursued a design called the multipurpose fiber optic transceiver (MFOX) and provided a family of fiber optic transceivers which operated up to 1 Gb/s. Currently, a second generation of high-speed fiber optic transceivers (HSFOX) is being developed. This design will utilize an all-integrated-circuits approach in order to develop a lighter-weight, smaller-size, and more efficient transceiver. The high-speed fiber optic transceiver will be military-and-space-operating in the 0.05-5 Gb/s data rate range. The initial results of tests, performance, and availability of commercial high-speed all-integrated-circuit chipsets for fiber-optic transceivers are discussed, as well as the performance of transceivers fabricated from these chipsets.

Hendricks, Herbert D.↗
NASA NTRS1972

Nondestructive testing of microtab welds

Introduction of sinusoidal signal across welded structure to determine reliability of integrated circuit connections is discussed. In-phase frequencies and quadrature frequency functions are used to evaluate weld reliability. Schematic diagram of test equipment and components is provided.

Feinstein, L.↗
NASA NTRS2018

Sixty Earth-Days Test of a Prototype Pt/HTCC Alumina Package in Simulated Venus Environment

This paper presents experimental results of a prototype high temperature co-fired ceramic (HTCC) package with Au/Pt metallization in a three-phase harsh environment test that culminated with 60-day demonstration in simulated Venus surface environment of 465 degC with corrosive atmosphere at 90 bar pressure. The prototype package is based on previously developed and reported HTCC package successfully tested with multiple analog and digital silicon carbide (SiC) high temperatures semiconductor integrated circuits (ICs) at NASA Glenn Research Center in 500 degC Earth air ambient for over ten thousands hours, and short-term tested at temperatures above 800 degC. The three-phase harsh environment test started with 48 hours in 465 degC Earth air, followed by 48 hours in 465 degC nitrogen at 90 bar pressure and 1400 hours in simulated Venus surface environment of 465 degC with corrosive atmosphere at 90 bar. Initial analytical results of the package materials and surfaces after exposure to Venus environment are discussed to assess the stability of the packaging materials in the tested environments. The test in simulated Venus environment was implemented in the NASA Glenn Extreme Environment Rig (GEER). The results of this study suggest that an effective encapsulation of areas of surface metallization and vicinities may help to improve electrical performance of a HTCC alumina packaging system in Venus environment.

Chen, Liangyu↗