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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.

DeGregorio, Kelly↗
DOE OSTI2024

Investigation on gate oxide reliability under gate bias screening for commercial SiC planar and trench MOSFETs

This paper evaluates the impact of the fast high gate-voltage screening technique on gate oxide reliability of commercial 1.2 kV 4H-SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The measurements are conducted on packaged devices with the intent that the results will be applicable to wafer-level screening. The threshold voltage (V th ) of SiC MOSFETs is measured before and after various screening treatments and recovery process. In addition, constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on SiC MOSFETs to obtain the intrinsic lifetime of gate oxide. The objective of this study is to determine the optimal screening conditions and improve screening efficiency without degradation of gate oxide reliability, such as V th shift and reduced oxide intrinsic lifetime. Due to the differences in the gate oxidation process and structural design of SiC planar and trench MOSFETs, the two types of devices exhibit different oxide reliability in the screening process. The recommended screening conditions obtained in this paper reveal that SiC trench MOSFETs can accept higher screening voltages compared to SiC planar MOSFETs. Hence, it can be concluded that more efficient screening techniques can be adopted for SiC MOSFETs with thicker gate oxide to meet the requirements of industrial applications.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Synthesis of Honeycomb-Structured Beryllium Oxide via Graphene Liquid Cells

Using high-resolution transmission electron microscopy and electron energy-loss spectroscopy, we demonstrate that beryllium oxide crystallizes in the planar hexagonal structure in a graphene liquid cell by a wet-chemistry approach. These liquid cells can feature van-der-Waals pressures up to 1 GPa, producing a miniaturized high-pressure container for the crystallization in solution. The thickness of as-received crystals is beyond the thermodynamic ultra-thin limit above which the wurtzite phase is energetically more favorable according to the theoretical prediction. The crystallization of the planar phase is ascribed to the near-free-standing condition afforded by the graphene surface. Our calculations show that the energy barrier of the phase transition is responsible for the observed thickness beyond the previously predicted limit. These findings open a new door for exploring aqueous-solution approaches of more metal-oxide semiconductors with exotic phase structures and properties in graphene-encapsulated confined cells.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS1991

Neutron, gamma ray and post-irradiation thermal annealing effects on power semiconductor switches

The effects of neutron and gamma rays on the electrical and switching characteristics of power semiconductor switches must be known and understood by the designer of the power conditioning, control, and transmission subsystem of space nuclear power systems. The SP-100 radiation requirements at 25 m from the nuclear source are a neutron fluence of 10(exp 13) n/sq cm and a gamma dose of 0.5 Mrads. Experimental data showing the effects of neutrons and gamma rays on the performance characteristics of power-type NPN Bipolar Junction Transistors (BJTs), Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), and Static Induction Transistors (SITs) are presented. These three types of devices were tested at radiation levels which met or exceeded the SP-100 requirements. For the SP-100 radiation requirements, the BJTs were found to be most sensitive to neutrons, the MOSFETs were most sensitive to gamma rays, and the SITs were only slightly sensitive to neutrons. Post-irradiation thermal anneals at 300 K and up to 425 K were done on these devices and the effectiveness of these anneals are also discussed.

Schwarze, G. E.↗
NASA NTRS2004

Fabrication of Channels for Nanobiotechnological Devices

A method, now undergoing development, of forming nanochannels in planar substrates is intended to enable the fabrication of advanced fluidic devices that could be integrated with complementary metal oxide semiconductor (CMOS) electronic circuits. Such integral combinations of fluidic and electronic components ("laboratory-on-a-chip" devices) could be used, for example, to detect individual molecules of deoxyribonucleic acid (DNA) and proteins. The width of a channel in such a device would be chosen so that molecules of the species of interest would move along the channel in single file. In this method, the fabrication of channels includes the use of such CMOS-compatible processes as chemical-mechanical polishing and oxide deposition. The layout of the channels in the substrate plane is determined by a single photolithographic process, but it is not a nanoscale lithographic process, and this process is not relied upon to define the thickness and width of the channels. Stating it from a slightly different perspective, unlike in the prior fabrication of electronic and fluidic devices involving the use of lithography to define microscale features, this process does not include the use of lithography to define nanoscale features. It is this aspect of the method that enables simplification of the process and, hence, a decrease in cost.

Lee, Choonsup↗
NASA NTRS2016

Long-Term Reliability of a Hard-Switched Boost Power Processing Unit Utilizing SiC Power MOSFETs

Silicon carbide (SiC) power devices have demonstrated many performance advantages over their silicon (Si) counterparts. As the inherent material limitations of Si devices are being swiftly realized, wide-band-gap (WBG) materials such as SiC have become increasingly attractive for high power applications. In particular, SiC power metal oxide semiconductor field effect transistors' (MOSFETs) high breakdown field tolerance, superior thermal conductivity and low-resistivity drift regions make these devices an excellent candidate for power dense, low loss, high frequency switching applications in extreme environment conditions. In this paper, a novel power processing unit (PPU) architecture is proposed utilizing commercially available 4H-SiC power MOSFETs from CREE Inc. A multiphase straight boost converter topology is implemented to supply up to 10 kilowatts full-scale. High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) characterization is performed to evaluate the long-term reliability of both the gate oxide and the body diode of the SiC components. Finally, susceptibility of the CREE SiC MOSFETs to damaging effects from heavy-ion radiation representative of the on-orbit galactic cosmic ray environment are explored. The results provide the baseline performance metrics of operation as well as demonstrate the feasibility of a hard-switched PPU in harsh environments.

Ikpe, Stanley A.↗
DOE OSTI2020

Layer-resolved ultrafast extreme ultraviolet measurement of hole transport in a Ni-TiO 2 -Si photoanode

Metal oxide semiconductor junctions are central to most electronic and optoelectronic devices, but ultrafast measurements of carrier transport have been limited to device-average measurements. Here, charge transport and recombination kinetics in each layer of a Ni-TiO 2 -Si junction is measured using the element specificity of broadband extreme ultraviolet (XUV) ultrafast pulses. After silicon photoexcitation, holes are inferred to transport from Si to Ni ballistically in ~100 fs, resulting in characteristic spectral shifts in the XUV edges. Meanwhile, the electrons remain on Si. After picoseconds, the transient hole population on Ni is observed to back-diffuse through the TiO 2 , shifting the Ti spectrum to a higher oxidation state, followed by electron-hole recombination at the Si-TiO 2 interface and in the Si bulk. Electrical properties, such as the hole diffusion constant in TiO 2 and the initial hole mobility in Si, are fit from these transient spectra and match well with values reported previously.

42 ENGINEERING↗
NASA NTRS2009

Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures over the range of -190 C to +225 C in terms of its voltage/current characteristic curves. The test temperatures included +22, -50, -100, -150, -175, -190, +50, +100, +150, +175, +200, and +225 C. Limited thermal cycling testing was also performed on the device. These tests consisted of subjecting the transistor to a total of twelve thermal cycles between -190 C and +225 C. A temperature rate of change of 10 C/min and a soak time at the test temperature of 10 minutes were used throughout this work. Post-cycling measurements were also performed at selected temperatures. In addition, re-start capability at extreme temperatures, i.e. power switched on while the device was soaking for a period of 20 minutes at the test temperatures of -190 C and +225 C, was investigated.

Patterson, Richard↗
DOE OSTI2020

Memristive Behavior Enabled by Amorphous–Crystalline 2D Oxide Heterostructure

The emergence of memristive behavior in amorphous–crystalline 2D oxide heterostructures, which are synthesized by atomic layer deposition (ALD) of a few-nanometer amorphous Al 2 O 3 layers onto atomically thin single-crystalline ZnO nanosheets, is demonstrated. The conduction mechanism is identified based on classic oxygen vacancy conductive channels. ZnO nanosheets provide a 2D host for oxygen vacancies, while the amorphous Al 2 O 3 facilitates the generation and stabilization of the oxygen vacancies. The conduction mechanism in the high-resistance state follows Poole–Frenkel emission, and in the the low-resistance state is fitted by the Mott–Gurney law. From the slope of the fitting curve, the mobility in the low-resistance state is estimated to be ≈2400 cm 2 V -1 s -1 , which is the highest value reported in semiconductor oxides. When annealed at high temperature to eliminate oxygen vacancies, Al is doped into the ZnO nanosheet, and the memristive behavior disappears, further confirming the oxygen vacancies as being responsible for the memristive behavior. The 2D heterointerface offers opportunities for new design of high-performance memristor devices.

2D heterostructures↗
DOE OSTI2023

Investigating the effect of aluminum oxide fixed charge on Schottky barrier height in molybdenum oxide-based selective contacts

A tunneling atomic layer deposited (ALD) AlO x layer was inserted in a Si|SiO x |AlO x |MoO x |metal tunnel diode structure to investigate the impact of fixed interface charge on Schottky barrier height. ALD AlO x provides a synthesis-tunable fixed charge and can provide excellent field effect passivation at the SiO x |AlO x interface. A large (>1 × 10 12 q.cm –2 ) negative fixed charge density was expected to decrease Schottky barrier height on p-type silicon and increase Schottky barrier height on n-type silicon by up to 0.4 eV based on an electrostatic model. Fixed charge density and interface trap state density were measured using a thick layer of AlO x in metal oxide semiconductor capacitor structures (MOSCAPs); Schottky barrier height and specific contact resistivity were measured using a tunneling-active layer of AlO x in contacted structures with MoO x . In some samples, HfO x interface layers were inserted between AlO x and silicon to quench the fixed negative charge. The Schottky barrier height was found to vary with processing conditions but did not have a strong correlation with expected fixed charge density. Here, while fixed charge may play a role in determining the Schottky barrier height, other parameters also have significant affect. Further work is needed to minimize contact resistivity and elucidate other factors impacting the Schottky barrier height.

14 SOLAR ENERGY↗
DOE OSTI2020

Phase-Exchange-Driven Wake-Up and Fatigue in Ferroelectric Hafnium Zirconium Oxide Films

Ferroelectric hafnium zirconium oxide holds great promise for a broad spectrum of complementary metal–oxide–semiconductor (CMOS) compatible and scaled microelectronic applications, including memory, low-voltage transistors, and infrared sensors, among others. An outstanding challenge hindering the implementation of this material is polarization instability during field cycling. Herein, the nanoscale phenomena contributing to both polarization fatigue and wake-up are reported. Using synchrotron X-ray diffraction, the conversion of non-polar tetragonal and polar orthorhombic phases to a non-polar monoclinic phase while field cycling devices comprising noble metal contacts is observed. This phase exchange accompanies a diminishing ferroelectric remanent polarization and provides device-scale crystallographic evidence of phase exchange leading to ferroelectric fatigue in these structures. A reduction in the full width at half-maximum of the superimposed tetragonal (101) and orthorhombic (111) diffraction reflections is observed to accompany wake-up in structures comprising tantalum nitride and tungsten electrodes. Combined with polarization and relative permittivity measurements, the observed peak narrowing and a shift in position to lower angles is attributed, in part, to a phase exchange of the non-polar tetragonal to the polar orthorhombic phase during wake-up. These results provide insight into the role of electrodes in the performance of hafnium oxide-based ferroelectrics and mechanisms driving wake-up and fatigue, and demonstrate a non-destructive means to characterize the phase changes accompanying polarization instabilities.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2023

Plasma-assisted deposition and characterization of Al 2 O 3 dielectric layers on (001) β -Ga 2 O 3

In this work, we have investigated plasma-assisted deposition of Al 2 O 3 on HVPE (001) β-Ga 2 O 3 and evaluated the dielectric quality from electrical measurements on fabricated metal-oxide-semiconductor (MOS) capacitors. The interface structure and crystallinity of the films were investigated as a function of the growth temperature. The dielectric/semiconductor interfaces were found to have reverse breakdown electric fields up to 5.3 MV/cm in the β-Ga 2 O 3 , with relatively low hysteresis in capacitance–voltage and low leakage current. We determined a negative fixed interface charge density at the interface from analysis of thickness-dependent capacitance voltage data. In conclusion, this study shows the advantage of using plasma-assisted deposition to achieve high breakdown strength Al 2 O 3 /β-Ga 2 O 3 MOS structures for device application purposes.

42 ENGINEERING↗
DOE OSTI2021

Exploiting Fixed Charge to Control Schottky Barrier Height in Si|Al 2 O 3 |MoO x – based Tunnel Diodes

The insertion of a tunneling atomic layer deposited (ALD) Al 2 O 3 film between MoO x and p-type Si has been studied to investigate Schottky barrier height tunability with varied negative fixed charge density. This work seeks to increase the hole-selectivity of MoO x -based contacts through manipulation of interface fixed charge. Fixed charge density and interface trap state densities are determined as a function of alumina processing conditions in metal-oxide-semiconductor capacitors (MOSCAPs). Schottky barrier heights were determined from Mott-Schottky analysis of tunnel diodes. An alumina deposition temperature of 80°C and post-deposition annealing at 425°C yielded the highest magnitude of negative fixed charge density (-3.5 × 10 12 q . cm –2 ). High deposition temperature and/or post-deposition annealing produced the lowest interface trap state density (1 × 10 12 eV -1 . cm –2 ). On p-type silicon, Schottky barrier height minimization was not clearly correlated with increasing fixed charge density. However, on n-type silicon, a significant increase in Schottky barrier height was evident (~0.8 eV to > 1 eV) and is attributed to the large negative fixed charge. Here, the findings from this work indicate that Schottky barrier height in carrier selective contacts can be tuned by electrostatic engineering of the SiO x |Al 2 O 3 interface.

aluminum oxide↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗
DOE OSTI2025

Radiation Response of Ga 2 O 3 MOSFETs Probed via Focused Particle Beams

Gallium Oxide (Ga 2 O 3 ), particularly in its β-phase, is attracting lots of interest for high-power and high-voltage electronics due to its wide bandgap, high breakdown field, and thermal stability. This study investigates the radiation response of Ga 2 O 3 Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) under Total Ionizing Dose (TID) and Displacement Damage (DD) conditions, which are critical for applications in radiation environments. Utilizing a dual-beam Focused Ion Beam and Scanning Electron Microscope setup, microscale analysis of radiation effects on individual devices is performed. The findings reveal distinct behaviors under TID and DD + TID conditions, with TID leading to threshold voltage shifts due to trapped charges, while DD results in decreased drive current attributed to increased carrier scattering from lattice defects. Notably, it is demonstrated that the TID effect can be mitigated through dynamic threshold voltage adjustments and that the predicted TID from ions calculated by Monte Carlo simulations overestimates actual TID due to unaccounted charge yield effects. In conclusion, this research enhances the understanding of Ga2O3 MOSFETs' performance in harsh radiation environments, providing insights for the design of robust electronic devices for space and nuclear applications.

MOSFET↗
DOE OSTI2026

Enhancing mobility and interface state engineering via UV-ozone treatment in BEOL-compatible ultrathin TiO 2 transistors

It has emerged as a potential candidate to improve the performance of monolithic-three-dimensional (M3D) integration of fused logic and memories through low-temperature in situ synthesis of high-performance metal–oxide–semiconductor (MOS) transistors. Here, we report the demonstration of the BEOL-compatible low thermal budget (350 °C) fabrication process of ultrathin-TiO2 transistors by the combination of RTA and UV-ozone treatment (RTA-UVOz). UV–ozone (UVOz) treatment of TiO2 anatase films significantly enhances stability, boosting ION current and field effect mobility (μ FE ) by two times of magnitude in TiO2 TFTs. UV ozone treatment helps to eliminate pre-existing oxygen vacancies and carbon contamination on TiO2 channels even at low temperature (100 °C), resulting in high-quality channel/dielectric interfaces with low interface states (D it ). During UVOz treatment, oxygen species (O x ) passivate the oxygen vacancies ($V$$^{2+}_{o}$), and hence low concentration of $V$$^{2+}_{o}$ would be left for ionization/de-ionization under PBS/NBS, leading to improved bias stress stability. Furthermore, the TiO 2 TFTs with thin ZrO 2 gate dielectric exhibited excellent performance including a lower subthreshold swing (SS) of 98 mV/dec with high drive I ON current ∼ 4.5 μA/μm, a high I ON /I OFF > 10 9 , and mobility μFE of 7 cm 2 /V-s under a battery powered voltage of 1 V. UV–ozone treatment enables high-performance, CMOS-compatible TiO 2 transistors with a low thermal budget, ideal for next-generation flexible, energy-efficient electronics.

BEOL↗
DOE OSTI2021

Electronically induced defect creation at semiconductor/oxide interface revealed by time-dependent density functional theory

Carrier induced defect creation at the semiconductor-oxide interface has been known as the origin of electronic device degradation for a long time, but how exactly the interface lattice can be damaged by carriers (especially low-energy ones) remains unclear. Here we carry out real-time time-dependent density functional theory simulations on concrete Si/SiO 2 interfaces to study the interaction between excited electrons and interface bonds. We show that the normal interface Si-H bonds are generally resistant to electrons due to the delocalized nature and high energy level of the Si-H antibonding states, and due to the high-energy barrier to break the Si-H bond. However, if an additional hydrogen atom exists by attaching to a nearby oxygen atom (forming a “Si-H···H-O” complex), the Si-H bond will be greatly weakened, including the reduction of energy barrier for bond breaking, and the lowering of the antibonding state energy level which favors electron injection. Together with the multiple vibrational excitation process, the corresponding Si-H bond can be broken much more easily. Thus we propose that the Si-H···H-O complex will be the center for defect creation and device degradation. Finally, we also explain why such a center might be relatively easy to form during the hydrogen annealing process.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗