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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

Software-Reconfigurable Processors for Spacecraft

A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

Farrington, Allen↗
NASA NTRS2012

CoNNeCT Baseband Processor Module Boot Code SoftWare (BCSW)

This software provides essential startup and initialization routines for the CoNNeCT baseband processor module (BPM) hardware upon power-up. A command and data handling (C&DH) interface is provided via 1553 and diagnostic serial interfaces to invoke operational, reconfiguration, and test commands within the code. The BCSW has features unique to the hardware it is responsible for managing. In this case, the CoNNeCT BPM is configured with an updated CPU (Atmel AT697 SPARC processor) and a unique set of memory and I/O peripherals that require customized software to operate. These features include configuration of new AT697 registers, interfacing to a new HouseKeeper with a flash controller interface, a new dual Xilinx configuration/scrub interface, and an updated 1553 remote terminal (RT) core. The BCSW is intended to provide a "safe" mode for the BPM when initially powered on or when an unexpected trap occurs, causing the processor to reset. The BCSW allows the 1553 bus controller in the spacecraft or payload controller to operate the BPM over 1553 to upload code; upload Xilinx bit files; perform rudimentary tests; read, write, and copy the non-volatile flash memory; and configure the Xilinx interface. Commands also exist over 1553 to cause the CPU to jump or call a specified address to begin execution of user-supplied code. This may be in the form of a real-time operating system, test routine, or specific application code to run on the BPM.

Yamamoto, Clifford K.↗
NASA NTRS2014

An Alternative Water Processor for Long Duration Space Missions

A new wastewater recovery system has been developed that combines novel biological and physicochemical components for recycling wastewater on long duration human space missions. Functionally, this Alternative Water Processor (AWP) would replace the Urine Processing Assembly on the International Space Station and reduce or eliminate the need for the multi-filtration beds of the Water Processing Assembly (WPA). At its center are two unique game changing technologies: 1) a biological water processor (BWP) to mineralize organic forms of carbon and nitrogen and 2) an advanced membrane processor (Forward Osmosis Secondary Treatment) for removal of solids and inorganic ions. The AWP is designed for recycling larger quantities of wastewater from multiple sources expected during future exploration missions, including urine, hygiene (hand wash, shower, oral and shave) and laundry. The BWP utilizes a single-stage membrane-aerated biological reactor for simultaneous nitrification and denitrification. The Forward Osmosis Secondary Treatment (FOST) system uses a combination of forward osmosis (FO) and reverse osmosis (RO), is resistant to biofouling and can easily tolerate wastewaters high in non-volatile organics and solids associated with shower and/or hand washing. The BWP has been operated continuously for over 300 days. After startup, the mature biological system averaged 85% organic carbon removal and 44% nitrogen removal, close to stoichiometric maximum based on available carbon. To date, the FOST has averaged 93% water recovery, with a maximum of 98%. If the wastewater is slighty acidified, ammonia rejection is optimal. This paper will provide a description of the technology and summarize results from ground-based testing using real wastewater

Barta, Daniel J.↗
NASA NTRS2015

A Biologically-Based Alternative Water Processor for Long Duration Space Missions

A wastewater recovery system has been developed that combines novel biological and physicochemical components for recycling wastewater on long duration space missions. Functionally, this Alternative Water Processor (AWP) would replace the Urine Processing Assembly on the International Space Station and reduce or eliminate the need for the multifiltration beds of the Water Processing Assembly (WPA). At its center are two unique game changing technologies: 1) a biological water processor (BWP) to mineralize organic forms of carbon and nitrogen and 2) an advanced membrane processor (Forward Osmosis Secondary Treatment) for removal of solids and inorganic ions. The AWP is designed for recycling larger quantities of wastewater from multiple sources expected during future exploration missions, including urine, hygiene (hand wash, shower, oral and shave) and laundry. The BWP utilizes a single-stage membrane-aerated biological reactor for simultaneous nitrification and denitrification. The Forward Osmosis Secondary Treatment (FOST) system uses a combination of forward osmosis (FO) and reverse osmosis (RO), is resistant to biofouling and can easily tolerate wastewaters high in non-volatile organics and solids associated with shower and/or hand washing. The BWP was operated continuously for over 300 days. After startup, the mature biological system averaged 85% organic carbon removal and 44% nitrogen removal, close to maximum based on available carbon. The FOST has averaged 93% water recovery, with a maximum of 98%. If the wastewater is slighty acidified, ammonia rejection is optimal. This paper will provide a description of the technology and summarize results from ground-based testing using real wastewater.

Barta, Daniel J.↗
NASA NTRS2018

Upgrades to the International Space Station Water Processor Assembly

The International Space Station Water Processor Assembly provides contaminant control and deionization to the Water Recovery System. The Water Processor Assembly presently utilizes sorbent-based Multifiltration Beds and a downstream Catalytic Reactor for these operations. Upgrades and process improvements are desired to improve performance, increase reliability, and decrease consumable resupply. To this end, reverse osmosis membrane separation technologies were evaluated to reduce influent contaminant loads, candidate additives to inhibit wastewater biofilm formation were studied, and life stability testing was completed for a recently developed high-activity catalyst. Evaluation of an adsorption media integration concept was also completed. The performance and applicability of these new technologies within the Water Processor Assembly, as well as their suitability for exploration missions, are discussed herein.

Kayatin, Matthew J.↗
NASA NTRSDate not supplied

Assembly and Integration Status of a High Fidelity Ground Test Bed for the Water Processor Assembly

The Water Recovery System (WRS) is a critical component of life support aboard the International Space Station (ISS) and will play an essential role in future missions beyond Low Earth Orbit (LEO). Its primary functional units – the Urine Processor Assembly (UPA), Brine Processor Assembly (BPA), and Water Processor Assembly (WPA) – must be evaluated for extended operation, dormancy resilience, material obsolescence, and reliability under exploration-driven constraints. Ground testing is vital for developing these technologies and generating statistically relevant reliability assessments, which requires extended runtime under integrated, Flight-like conditions. Currently, no high-fidelity, fully integrated WPA ground test bed exists to support these objectives. To address this gap, NASA is developing a WPA test bed at Marshall Space Flight Center (MSFC) that combines downgraded ISS flight hardware with functionally flight-like components in a cost-effective configuration while maintaining priority hardware investigations. This paper describes the current status of hardware assembly and integration, outlines key challenges such as simulating microgravity effects and mitigating obsolescence, and presents future test objectives including software development, reliability assessments, dormancy studies, and exploration-oriented upgrades.

Mary-Elizabeth Davis↗
NASA NTRS1992

An Analog Processor for Image Compression

This paper describes a novel analog Vector Array Processor (VAP) that was designed for use in real-time and ultra-low power image compression applications. This custom CMOS processor is based architectually on the Vector Quantization (VQ) algorithm in image coding, and the hardware implementation fully exploits the inherent parallelism built-in the VQ algorithm.

Vector Array Processor VAP analog processor image ↗
NASA NTRS2004

On-board processor for direct distribution of change detection data products

We are developing an on-board imagin radar data processor for repeat-pass change detection and hazards management. This is the enabling technology for NASA ESE to utilize imaging radars. This processor will enable the observation and use of surface deformation data over rapidly evolving natural hazards, both as an aid to scientific understanding ad to provide timely data to agencies responsible for the management and mitigation of natural disasters.

InSAR↗
NASA NTRS2012

Fault Mitigation Schemes for Future Spaceflight Multicore Processors

Future planetary exploration missions demand significant advances in on-board computing capabilities over current avionics architectures based on a single-core processing element. The state-of-the-art multi-core processor provides much promise in meeting such challenges while introducing new fault tolerance problems when applied to space missions. Software-based schemes are being presented in this paper that can achieve system-level fault mitigation beyond that provided by radiation-hard-by-design (RHBD). For mission and time critical applications such as the Terrain Relative Navigation (TRN) for planetary or small body navigation, and landing, a range of fault tolerance methods can be adapted by the application. The software methods being investigated include Error Correction Code (ECC) for data packet routing between cores, virtual network routing, Triple Modular Redundancy (TMR), and Algorithm-Based Fault Tolerance (ABFT). A robust fault tolerance framework that provides fail-operational behavior under hard real-time constraints and graceful degradation will be demonstrated using TRN executing on a commercial Tilera(R) processor with simulated fault injections.

software based↗
NASA NTRS1999

ELIPS: Toward a Sensor Fusion Processor on a Chip

The paper presents the concept and initial tests from the hardware implementation of a low-power, high-speed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) processor is developed to seamlessly combine rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor in compact low power VLSI.

sensor↗
NASA NTRS1996

An Automated Mapping Processor Using C-Band Interferometric SAR Data

We present the description of a processor which has been implemented to generate map products starting from C-band interferometric data. The first stage of the processor consists of the conventional interferometric SAR processing producing a Digital Elevation Model (DEMs) and a SAR brightness image in sensor coordinates.

processor↗
NASA NTRS1998

The NASA/JPL AIRSAR Integrated Processor

The NASA/JPL AIRSAR Integrated Processor (AIP) is a multi-frequency polarimetric and interferometric SAR processor designed for better understanding of scattering from different types of Earth terrain.

AIRSAR↗
NASA NTRS1967

A conceptual, parallel operating data compression processor

Data compressor processor concept envisions a simplified system for telemetry communications. It is simultaneously a zero-order processor and a floating aperture, a variable aperture, and a binary integer aperture with a decoded buffet fullness counter.

Anderson, T. O.↗
NASA NTRS1972

Radio astronomy Explorer B antenna aspect processor

The antenna aspect system used on the Radio Astronomy Explorer B spacecraft is described. This system consists of two facsimile cameras, a data encoder, and a data processor. Emphasis is placed on the discussion of the data processor, which contains a data compressor and a source encoder. With this compression scheme a compression ratio of 8 is achieved on a typical line of camera data. These compressed data are then convolutionally encoded.

Miller, W. H.↗
NASA NTRS1975

Improved general-purpose namelist processor

Processor is written in FORTRAN with minimal machine-dependent coding, allowing easy conversion to various digital computers. It eliminates 19 continuation-card limit of current namelist processors and permits unlimited number of variables to be read in a single namelist declaration.

Wojtaszek, E. W.↗