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Two-stage inverter includes variable-frequency, voltage-regulating first stage and fixed-frequency second stage. Lightweight circuit provides regulated power and is invulnerable to output short circuits. Does not require large capacitor across ac bus, like parallel resonant designs. Particularly suitable for use in ac-power-distribution system of aircraft.
Only two of four switches interrupt substantial current. An asymmetric timing scheme improves design and operation of pulse-width-modulation (PWM) H-bridge switch-and-transformer circuit. Circuit part of dc-to-dc converter or dc-to-ac inverter; in either case, output current or voltage regulated by adjusting times of opening and closing of semiconductor switches 1 through 4 to adjust durations of current pulses in primary winding of transformer.
The design of the High Voltage Power Converter Unit on DS1 allows both the spacecraft avionics and ion propulsion to operate in a stable manner near the PPP of the solar array. This approach relies on a fairly well-defined solar array model to determine the projected PPP. The solar array voltage set-points have to be updated every week to maintain operation near PPP. Stable operation even to the LEFT of the Peak Power Point is achievable so long as you do not change the operating power level of the ion engine. The next step for this technology is to investigate the use of onboard autonomy to determine the optimum SA voltage regulation set-point (i.e. near the PPP); this is for future missions that have one or more ion propulsion subsystems.
Power converters capable of operation at cryogenic temperatures are anticipated to play an important role in the power system architecture of future NASA deep space missions. Design of such converters to survive cryogenic temperatures will improve the power system performance and reduce development and launch costs. Aerospace power systems are mainly a DC distribution network. Therefore, DC/DC and DC/AC converters provide the outputs needed to different loads at various power levels. Recently, research efforts have been performed at the NASA Glenn Research Center (GRC) to design and evaluate DC/DC converters that are capable of operating at cryogenic temperatures. This paper presents a summary of the research performed to evaluate the low temperature performance of five DC/DC converters. Various parameters were investigated as a function of temperature in the range of 20 to -196 C. Data pertaining to the output voltage regulation and efficiency of the converters is presented and discussed.
The propulsion system of the Microwave Anisotropy Probe (MAP) had stringent requirements that made the thermal design unique. To meet instrument stability requirements the system had to be designed to keep temperatures of all components within acceptable limits without heater cycling. Although the spacecraft remains at a fixed 22 sun angle at L2, the variations in solar constant, property degradation, and bus voltage range all significantly affect the temperature. Large portions of the fuel lines are external to the structure and all components are mounted to non-conductive composite structure. These two facts made the sensitivity to the MLI effective emissivity and bus temperature very high. Approximately two years prior to launch the propulsion system was redesigned to meet MAP requirements. The new design utilized hardware that was already installed in order to meet schedule constraints. The spacecraft design and the thermal requirements were changed to compensate for inadequacies of the existing hardware. The propulsion system consists of fuel lines, fill and drain lines/valve, eight thrusters, a HXCM, and a propulsion tank. A voltage regulator was added to keep critical components within limits. Software was developed to control the operational heaters. Trim resistors were put in series with each operational heater circuits and the tank survival heater. A highly sophisticated test program, which included real time model correlation, was developed to determine trim resistors sizes. These trim resistors were installed during a chamber break and verified during thermal balance testing.
An amplifier developed under a Small Business Innovation Research (SBIR) contract will have applications for both satellite and terrestrial communications. This power amplifier uses an innovative series bias arrangement of active devices to achieve over 40-percent efficiency at Ka-band frequencies with an output power of 0.66 W. The amplifier is fabricated on a 2.0- by 3.8-square millimeter chip through the use of Monolithic Microwave Integrated Circuit (MMIC) technology, and it uses state-of-the-art, Pseudomorphic High-Electron-Mobility Transistor (PHEMT) devices. Although the performance of the MMIC chip depends on these high-performance devices, the real innovations here are a unique series bias scheme, which results in a high-voltage chip supply, and careful design of the on-chip planar output stage combiner. This design concept has ramifications beyond the chip itself because it opens up the possibility of operation directly from a satellite power bus (usually 28 V) without a dc-dc converter. This will dramatically increase the overall system efficiency. Conventional microwave power amplifier designs utilize many devices all connected in parallel from the bias supply. This results in a low-bias voltage, typically 5 V, and a high bias current. With this configuration, substantial I(sup 2) R losses (current squared times resistance) may arise in the system bias-distribution network. By placing the devices in a series bias configuration, the total current is reduced, leading to reduced distribution losses. Careful design of the on-chip planar output stage power combiner is also important in minimizing losses. Using these concepts, a two-stage amplifier was designed for operation at 33 GHz and fabricated in a standard MMIC foundry process with 0.20-m PHEMT devices. Using a 20-V bias supply, the amplifier achieved efficiencies of over 40 percent with an output power of 0.66 W and a 16-dB gain over a 2-GHz bandwidth centered at 33 GHz. With a 28-V bias, a power level of 1.1 W was achieved with a 12-dB gain and a 36-percent efficiency. This represents the best reported combination of power and efficiency at this frequency. In addition to delivering excellent power and gain, this Ka-band MMIC power amplifier has an efficiency that is 10 percent greater than existing designs. The unique design offers an excellent match for spacecraft applications since the amplifier supply voltage is closely matched to the typical value of spacecraft bus voltage. These amplifiers may be used alone in applications of 1 W or less, or several may be combined or used in an array to produce moderate power, Ka-band transmitters with minimal power combining and less thermal stress owing to the combination of excellent efficiency and power output. The higher voltage operation of this design may also save mass and power because the dc-dc power converter is replaced with a simpler voltage regulator.
THE BAT is the primary instrument on the Swift spacecraft. The Swift mission is part of the National Aeronautics and Space Administration (NASA) Medium-Size Explorer (MIDEX) Program, and is managed by Goddard Space Flight Center (GSFC). It is designed to detect gamma ray burst over a broad region of the sky in a low Earth orbit of 600-km altitude and quickly align the telescopes on the spacecraft to the gamma ray source. It was successfully launched into orbit on November 20, 2004. The Swift mission is a first of its kind of multi-wavelength transient observatory for gamma ray burst astronomy. Its mission life is 2 years. The inclination is 22 deg maximum. The spacecraft bus voltage to the instruments is in the 24 V to 35 V range. The instruments will be turned off when the voltage is below 27 V. The BAT is mounted to the optical bench through five titanium flexures. The BAT has been developed at GSFC. Its telescope assembly consists of 256 Detector Modules (DMs) in the Detector Array. There are 16 Detector Array Blocks. Each Block holds 16 DMs, 3 Block Voltage Regulator (BVR) units and 3 Block Command & Data Handling (BCDH) units. The power dissipation of each Block has been measured to be 13 W. Therefore the total power dissipation of the 16 Blocks is 208 W. The DAP is 1.3 m (4.3 ft) x 1 m (3.3 ft), accommodates all the 16 Blocks. It also provides the mounting surface and the positional stability for the Blocks. The DMs are located at the top (+X side) of the DAP and is enclosed by graded-Z shields on the sides and a coded mask at the top. The BVRs and BCDHs are located at the bottom (-X side) of the DAP. Eight Blocks are located at the front (-Z side or radiator side) of the DAP, and eight are located at the rear (+Z side) of the DAP. The DMs and top of DAP are insulated with a 7-layer multi-layer insulation (MLI). There is a 5.08 cm (2 in) x 5.08 cm (2 in) MLI cutout over each Block heater controller so that heat radiates from the heater controller to the mask. The exterior of the mask, graded-Z shields and bottom of DAP is insulated with a 15-layer MLI.
The use of bipolar linear devices is prevalent in most satellite and some space applications. However, degradation as a result of low dose irradiations known as ELDERS (effects of enhanced low dose rate sensitivity) is a major concern when selecting flight hardware. Many studies and reports have been conducted on this possible phenomenon as well as their responsible physical mechanisms.
Total dose tests of several bipolar linear devices show sensitivity to both dose rate and bias during exposure. All devices exhibited Enhanced Low Dose Rate Sensitivity (ELDRS). An accelerated ELDRS test method for three different devices demonstrate results similar to tests at low dose rate. Behavior and critical parameters from these tests are compared and discussed.
We present results on the effects on ELDRS at dose rates of 10, 5, 1, and 0.5 mrad(Si)/s for a variety of radiation hardened and commercial devices. We observed low dose rate enhancement below 10 mrad(Si)/s in several different parts. The magnitudes of the dose rate effects vary. The TL750L, a commercial voltage regulator, showed dose rate dependence in the functional failures, with initial failures occurring after 10 krad(Si) for the parts irradiated at 0.5 mrad(Si)/s. The RH1021 showed an increase in low dose rate enhancement by 2x at 5 mrad(Si)/s relative to 8 mrad(Si)/s and high dose rate, and parametric failure after 100 krad(Si). Additionally the ELDRS-free devices, such as the LM158 and LM117, showed evidence of dose rate sensitivity in parametric degradations. Several other parts also displayed dose rate enhancement, with relatively lower degradations up to approx.15 to 20 krad(Si). The magnitudes of the dose rate enhancement will likely increase in significance at higher total dose levels.
The Digital Beamforming Synthetic Aperture Radar (DBSAR) is an eight-channel phased array radar system that employs solid-state radar transceivers, a microstrip patch antenna, and a reconfigurable waveform generator and processor unit. The original DBSAR transceiver design utilizes connectorized electronic components that tend to be physically large and heavy. To achieve increased functionality in a smaller volume, PCB (printed circuit board) transceivers were designed to replace the large connectorized transceivers. One of the most challenging problems designing the transceivers in a PCB format was achieving proper performance in the calibration path. For a radar loop-back calibration path, a portion of the transmit signal is coupled out of the antenna feed and fed back into the receiver. This is achieved using passive components for stability and repeatability. Some signal also leaks through the receive path. As these two signal paths are correlated via an unpredictable phase, the leakage through the receive path during transmit must be 30 dB below the calibration path. For DBSAR s design, this requirement called for a 100-dB isolation in the receiver path during transmit. A total of 16 solid-state L-band transceivers on a PCB format were designed. The transceivers include frequency conversion stages, T/R switching, and a calibration path capable of measuring the transmit power-receiver gain product during transmit for pulse-by-pulse calibration or matched filtering. In particular, this calibration path achieves 100-dB isolation between the transmitted signal and the low-noise amplifier through the use of a switching network and a section of physical walls achieving attenuation of radiated leakage. The transceivers were designed in microstrip PCBs with lumped elements and individually packaged components for compactness. Each transceiver was designed on a single PCB with a custom enclosure providing interior walls and compartments to isolate transceiver subsystems from radiated interference. The enclosure also acts as a heat sink for the voltage regulators and power amplifiers inside the system. The PCB transceiver design produces transmit pulses of 2 W with an arbitrary duty cycle. Each transceiver is fed by an external 120-MHz signal transmit and two 1,140-MHz local oscillator signals. The received signal is amplified and down-converted to 120 MHz and is fed to the data processor. The transceiver dimensions are approximately 3.5 11.5 0.6 in. (9 29 1.5 cm). The PCB transceiver design reduces the volume and weight of the DBSAR instrument while maintaining the functionality found in the original design. Both volume and weight are critical for airborne and flight remote sensing instrumentation.
This paper details the design architecture, design methodology, and the advantages of the SpaceCube v2.0 high performance data processing system for space applications. The purpose in building the SpaceCube v2.0 system is to create a superior high performance, reconfigurable, hybrid data processing system that can be used in a multitude of applications including those that require a radiation hardened and reliable solution. The SpaceCube v2.0 system leverages seven years of board design, avionics systems design, and space flight application experiences. This paper shows how SpaceCube v2.0 solves the increasing computing demands of space data processing applications that cannot be attained with a standalone processor approach.The main objective during the design stage is to find a good system balance between power, size, reliability, cost, and data processing capability. These design variables directly impact each other, and it is important to understand how to achieve a suitable balance. This paper will detail how these critical design factors were managed including the construction of an Engineering Model for an experiment on the International Space Station to test out design concepts. We will describe the designs for the processor card, power card, backplane, and a mission unique interface card. The mechanical design for the box will also be detailed since it is critical in meeting the stringent thermal and structural requirements imposed by the processing system. In addition, the mechanical design uses advanced thermal conduction techniques to solve the internal thermal challenges.The SpaceCube v2.0 processing system is based on an extended version of the 3U cPCI standard form factor where each card is 190mm x 100mm in size The typical power draw of the processor card is 8 to 10W and scales with application complexity. The SpaceCube v2.0 data processing card features two Xilinx Virtex-5 QV Field Programmable Gate Arrays (FPGA), eight memory modules, a monitor FPGA with analog monitoring, Ethernet, configurable interconnect to the Xilinx FPGAs including gigabit transceivers, and the necessary voltage regulation. The processor board uses a back-to-back design methodology for common parts that maximizes the board real estate available. This paper will show how to meet the IPC 6012B Class 3A standard with a 22-layer board that has two column grid array devices with 1.0mm pitch. All layout trades such as stack-up options, via selection, and FPGA signal breakout will be discussed with feature size results. The overall board design process will be discussed including parts selection, circuit design, proper signal termination, layout placement and route planning, signal integrity design and verification, and power integrity results. The radiation mitigation techniques will also be detailed including configuration scrubbing options, Xilinx circuit mitigation and FPGA functional monitoring, and memory protection.Finally, this paper will describe how this system is being used to solve the extreme challenges of a robotic satellite servicing mission where typical space-rated processors are not sufficient enough to meet the intensive data processing requirements. The SpaceCube v2.0 is the main payload control computer and is required to control critical subsystems such as autonomous rendezvous and docking using a suite of vision sensors and object avoidance when controlling two robotic arms.
Returning samples from Low Earth Orbit (LEO) is no simple task. Whether the samples are scientific experiments or surveillance footage, engineers must overcome many challenges to achieve mission success. In August of 1960 the first payload recovered from LEO, the Corona capsule, carried “more photographic coverage of the Soviet Union than all previous U-2 missions”. The Corona program proved that re-turning surveillance footage from LEO is possible, the program is still referenced today when designing new sample return missions. Although there are many crucial subsystems that make up a sample return capsule, the avionics subsystem demands the most attention. This paper will discuss how current CubeSat avionics components can be applied to large sample return missions. One advantage of using CubeSat avionics components is that they can fit into a 1.5 U (10x10x15 cm) compartment, leaving more room for the payload. This paper is broken down as follows. First, the reader is introduced to the history of sample return projects. The major design strengths of previous projects are analyzed and applied to the current capsule design. Next, the typical trajectory of a capsule is presented along with mission requirements and operations. During the re-entry phase, the avionics subsystem is responsible for commanding the deployment of the parachute, back shell, and the heat shield. Next, the power subsystem is discussed in detail including a trade study on batteries and voltage regulators. Next, the interface between the Ground Support Equipment (GSE) and the avionics components is discussed. It is important that the capsule is able to provide avionics system state of health to ensure proper functionality before the capsule is launched. Next, an in-depth analysis of current TechEdSat avionics components, with proven flight history, are presented. The various avionics components including the radios, GPS, IMU, temperature sensors, altitude sensors, and ejectors are discussed. The application of cur-rent avionics components to a sample return projects are analyzed. After, the wiring diagram is presented along with a discussion of the design. Next, a summary of how the avionics components are tested and validated is pro-vided. Finally, this article will present current sample return missions TechEdSat avionics components are being applied to. CubeSat Avionics can be applied to almost all sample return missions due to their compact configuration and proven space flight heritage. The TechEdSat team is currently making great progress in returning samples from the International Space Station (ISS) and is excited to present how their avionics components can be applied to a full-scale sample return mission.
This paper reports recent single-event latchup results for a variety of microelectronic devices that include an ADC, OpAmp, EEPROM, CPLD, PWM, transceiver, voltage regulator, digital signal processor, step-down converter, buck controller and supervisory circuits. The data were collected to evaluate these devices for possible use in NASA ISS payloads.
The Vorago Technologies RH-OBC-1 is a CubeSat Kit Bus compatible single board computer with a Vorago VA10820 ARM Cortex-M0 microcontroller at its core. The board also includes a set of common peripheral integrated circuits, like voltage regulators, non-volatile memories (NVM), an analog-to-digital converter (ADC), a watchdog/supervisor, and a Controller Area Network (CAN) bus transceiver. High-energy proton (200 MeV) testing was conducted at both board and component levels to investigate single-event effects.
Computing capabilities of space systems have in-creased onboard performance by orders of magnitude with the use of radiation-tolerant field-programmable gate arrays (FPGA)and processors. The incorporation of signal and power integrity analysis with printed circuit board (PCB) design in reliable computing architectures for space systems has become critical to enable future mission capabilities. Developers launch high-performance processors into a breadth of orbits and missions, running varying applications that create challenges for designing reliable computing hardware. Specifically, for these designs, academic and industry research has focused on component radiation performance, fault mitigation, and reliable architectures. How-ever, other design parameters including electromagnetic interference (EMI), PCB stackup, signal integrity (SI), voltage regulator module (VRM) design, and power distribution network (PDN)are often deprioritized or disregarded as the design matures. Since these characteristics are becoming more significant in high-performance processor designs, this research presents a hardware design and analysis methodology for high-performance, space-computing systems that focuses on a holistic design approach and PDN reliability. While these challenges exist across all space hardware, the reduced PCB dimensions imposed by SmallSats and CubeSats introduce additional hurdles, specifically to VRM and decoupling design. By examining the relationship between the PDN and radiation performance, an analytical relationship is developed that incorporates Total Ionizing Dose and Single-Event Transients to ensure reliability throughout the mission duration. The presented design methodology is applied to the SpaceCube v3.0 Mini, an FPGA-based on-board science data processing system developed at NASA Goddard Space Flight Center.
Dc to dc static power conditioning systems on unmanned spacecraft have as their inputs highly fluctuating dc voltages which they condition to regulated dc voltages. These input voltages may be less than or greater than the desired regulated voltages. The design of two circuits which address specific problems in the design of these power conditioning systems and a nonlinear analysis of one of the circuits are discussed. The first circuit design is for a nondissipative active ripple filter which uses an operational amplifier to amplify and cancel the sensed ripple voltage. A dc to dc converter operating at a switching frequency of 1 MHz is the second circuit discussed. A nonlinear analysis of the type of dc to dc converter utilized in designing the 1 MHz converter is included.
DC-to-DC prime converter for anchored interplanetary monitoring platform spacecraft /AIMP/ transforming power from solar array into suitable level for instrumentation electronics