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At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

Biodosimetry as a New Paradigm for Determination of Radiation Risks and Risk-Mitigation in Astronauts Exposed to Space Radiation

Predicting risk of cancer in astronauts exposed to space radiation is challenging partly because uncertainties of absorption of dose and the processing of dose-related damage at the cellular level degrade the confidence of predicting the expression of cancer. Cellular biodosimeters that simultaneously report: 1) the quantity of absorbed dose after exposure to ionizing radiation, 2) the quality of radiation delivering that dose, and 3) the macromolecular profiles related to malignant transformation in cells absorbing that dose would therefore be useful. An approach to such a multiparametric biodosimeter will be reported, This is the demonstration of two dose-responsive field-effects of enhanced protein-expression. In one case, expression of keratin 18 (K18) in cultures of human mammary epithelial cells (HMEC) irradiated with cesium-137 gamma-rays is enhanced following exposure of log phase cells to relatively low doses of 30 to 90 cGy. K18 has been reported by a marker for tumor staging and for apoptosis. In the second case, expression of connexin 43 (Cx43) is increased in irradiated stationary phase cultures of HMEC, indicating enhanced formation of gap junctions. Gap junctions have been reported to be involved in bystander effects following irradiation. It is a biodosimeter for assessing radiogenic damage. It is suggested further that such biomolecular dosimetry may introduce a new paradigm for assessing cancer risk and risk-mitigation in individuals, a requirement for managing radiation health in astronauts during extended missions in space. This new paradigm is built upon the statistical power provided by the use of functional genomics and proteomics represented in combined gene- and protein-expression assays.

Richmond, Robert↗
NASA NTRS2002

Low-Loss, High-Isolation Microwave Microelectromechanical Systems (MEMS) Switches Being Developed

Switches, electrical components that either permit or prevent the flow of electricity, are the most important and widely used electrical devices in integrated circuits. In microwave systems, switches are required for switching between the transmitter and receiver; in communication systems, they are needed for phase shifters in phased-array antennas, for radar and communication systems, and for the new class of digital or software definable radios. Ideally, switches would be lossless devices that did not depend on the electrical signal's frequency or power, and they would not consume electrical power to change from OFF to ON or to maintain one of these two states. Reality is quite different, especially at microwave frequencies. Typical switches in microwave integrated circuits are pin diodes or gallium arsenide (GaAs) field-effect transistors that are nonlinear, with characteristics that depend on the power of the signal. In addition, they are frequency-dependent, lossy, and require electrical power to maintain a certain state. A new type of component has been developed that overcomes most of these technical difficulties. Microelectromechanical (MEMS) switches rely on mechanical movement as a response to an applied electrical force to either transmit or reflect electrical signal power. The NASA Glenn Research Center has been actively developing MEMS for microwave applications for over the last 5 years. Complete fabrication procedures have been developed so that the moving parts of the switch can be released with near 100-percent yield. Moreover, the switches fabricated at Glenn have demonstrated state-of-the-art performance. A typical MEMS switch is shown. The switch extends over the signal and ground lines of a finite ground coplanar waveguide, a commonly used microwave transmission line. In the state shown, the switch is in the UP state and all the microwave power traveling along the transmission line proceeds unimpeded. When a potential difference is applied between the cantilever and the transmission line, the cantilever is pulled downward until it connects the signal line to the ground planes, creating a short circuit. In this state, all the microwave power is reflected. The graph shows the measured performance of the switch, which has less than 0.1 dB of insertion loss and greater than 30dB of isolation. These switches consume negligible electrical power and are extremely linear. Additional research is required to address reliability and to increase the switching speed.

Ponchak, George E.↗
NASA NTRS1983

FET commutated current-FED inverter

A shunt switch comprised of a field-effect transistor (Q.sub.1) is employed to commutate a current-fed inverter (10) using thyristors (SCR1, SCR2) or bijunction transistors (Q.sub.2, Q.sub.3) in a full bridge (1, 2, 3, 4) or half bridge (5, 6) and transformer (T.sub.1) configuration. In the case of thyristors, a tapped inverter (12) is employed to couple the inverter to a dc source to back bias the thyristors during commutation. Alternatively, a commutation power supply (20) may be employed for that purpse. Diodes (D.sub.1, D.sub.2) in series with some voltage dropping element (resistor R.sub.12 or resistors R.sub.1, R.sub.2 or Zener diodes D.sub.4, D.sub.5) are connected in parallel with the thyristors in the half bridge and transformer configuration to assure sharing the back bias voltage. A clamp circuit comprised of a winding (18) negatively coupled to the inductor and a diode (D.sub.3) return stored energy from the inductor to the power supply for efficient operation with buck or boost mode.

Rippel, Wally E.↗
NASA NTRS1989

Thin film memory matrix using amorphous and high resistive layers

Memory cells in a matrix are provided by a thin film of amorphous semiconductor material overlayed by a thin film of resistive material. An array of parallel conductors on one side perpendicular to an array of parallel conductors on the other side enable the amorphous semiconductor material to be switched in addressed areas to be switched from a high resistance state to a low resistance state with a predetermined level of electrical energy applied through selected conductors, and thereafter to be read out with a lower level of electrical energy. Each cell may be fabricated in the channel of an MIS field-effect transistor with a separate common gate over each section to enable the memory matrix to be selectively blanked in sections during storing or reading out of data. This allows for time sharing of addressing circuitry for storing and reading out data in a synaptic network, which may be under control of a microprocessor.

Thakoor, Anilkumar P.↗
NASA NTRS2008

Vertical Isolation for Photodiodes in CMOS Imagers

In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

Pain, Bedabrata↗
NASA NTRS2006

FETs Based on Doped Polyaniline/Polyethylene Oxide Fibers

A family of experimental highly miniaturized field-effect transistors (FETs) is based on exploitation of the electrical properties of nanofibers of polyaniline/ polyethylene oxide (PANi/PEO) doped with camphorsulfonic acid. These polymer-based FETs have the potential for becoming building blocks of relatively inexpensive, low-voltage, highspeed logic circuits that could supplant complementary metal oxide/semiconductor (CMOS) logic circuits. The development of these polymerbased FETs offers advantages over the competing development of FETs based on carbon nanotubes. Whereas it is difficult to control the molecular structures and, hence, the electrical properties of carbon nanotubes, it is easy to tailor the electrical properties of these polymerbased FETs, throughout the range from insulating through semiconducting to metallic, through choices of doping levels and chemical manipulation of polymer side chains. A further advantage of doped PANi/PEO nanofibers is that they can be made to draw very small currents and operate at low voltage levels, and thus are promising for applications in which there are requirements to use many FETs to obtain large computational capabilities while minimizing power demands. Fabrication of an experimental FET in this family begins with the preparation of a substrate as follows: A layer of silicon dioxide between 50 and 200 nm thick is deposited on a highly doped (resistivity 0.01 W.cm) silicon substrate, then gold electrodes/contact stripes are deposited on the oxide. Next, one or more fibers of camphorsulphonic acid-doped PANi/PEO having diameters of the order of 100 nm are electrospun onto the substrate so as to span the gap between the gold electrodes (see Figure 1). Figure 2 depicts measured current-versus-voltage characteristics of the device of Figure 1, showing that saturation channel currents occur at source-todrain potentials that are surprisingly low, relative to those of CMOS FETs. The hole mobility in the depletion regime in this transistor was found to be 1.4 10(exp -4) sq cm/(V.s), while the one-dimensional charge density at zero gate bias was estimated to be approximately one hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content of the fibers is expected to enhance the properties of future versions of this transistor.

Theofylaktos, Noulie↗
NASA NTRS2005

X-Band, 17-Watt Solid-State Power Amplifier

An advanced solid-state power amplifier that can generate an output power of as much as 17 W at a design operating frequency of 8.4 GHz has been designed and constructed as a smaller, lighter, less expensive alternative to traveling-wave-tube X-band amplifiers and to prior solid-state X-band power amplifiers of equivalent output power. This amplifier comprises a monolithic microwave integrated circuit (MMIC) amplifier module and a power-converter module integrated into a compact package (see Figure 1). The amplifier module contains an input variable-gain amplifier (VGA), an intermediate driver stage, a final power stage, and input and output power monitors (see Figure 2). The VGA and the driver amplifier are 0.5-m GaAs-based metal semiconductor field-effect transistors (MESFETs). The final power stage contains four parallel high-efficiency, GaAs-based pseudomorphic high-electron-mobility transistors (PHEMTs). The gain of the VGA is voltage-variable over a range of 10 to 24 dB. To provide for temperature compensation of the overall amplifier gain, the gain-control voltage is generated by an operational-amplifier circuit that includes a resistor/thermistor temperature-sensing network. The driver amplifier provides a gain of 14 dB to an output power of 27 dBm to drive the four parallel output PHEMTs, each of which is nominally capable of putting out as much as 5 W. The driver output is sent to the input terminals of the four parallel PHEMTs through microstrip power dividers; the outputs of these PHEMTs are combined by microstrip power combiners (which are similar to the microstrip power dividers) to obtain the final output power of 17 W.

Mittskus, Anthony↗
NASA NTRS2005

Series-Connected Buck Boost Regulators

A series-connected buck boost regulator (SCBBR) is an electronic circuit that bucks a power-supply voltage to a lower regulated value or boosts it to a higher regulated value. The concept of the SCBBR is a generalization of the concept of the SCBR, which was reported in "Series-Connected Boost Regulators" (LEW-15918), NASA Tech Briefs, Vol. 23, No. 7 (July 1997), page 42. Relative to prior DC-voltage-regulator concepts, the SCBBR concept can yield significant reductions in weight and increases in power-conversion efficiency in many applications in which input/output voltage ratios are relatively small and isolation is not required, as solar-array regulation or battery charging with DC-bus regulation. Usually, a DC voltage regulator is designed to include a DC-to-DC converter to reduce its power loss, size, and weight. Advances in components, increases in operating frequencies, and improved circuit topologies have led to continual increases in efficiency and/or decreases in the sizes and weights of DC voltage regulators. The primary source of inefficiency in the DC-to-DC converter portion of a voltage regulator is the conduction loss and, especially at high frequencies, the switching loss. Although improved components and topology can reduce the switching loss, the reduction is limited by the fact that the converter generally switches all the power being regulated. Like the SCBR concept, the SCBBR concept involves a circuit configuration in which only a fraction of the power is switched, so that the switching loss is reduced by an amount that is largely independent of the specific components and circuit topology used. In an SCBBR, the amount of power switched by the DC-to-DC converter is only the amount needed to make up the difference between the input and output bus voltage. The remaining majority of the power passes through the converter without being switched. The weight and power loss of a DC-to-DC converter are determined primarily by the amount of power processed. In the SCBBR, the unswitched majority of the power is passed through with very little power loss, and little if any increase in the sizes of the converter components is needed to enable the components to handle the unswitched power. As a result, the power-conversion efficiency of the regulator can be very high, as shown in the example of Figure 1. A basic SCBBR includes a DC-to-DC converter (see Figure 2). The switches and primary winding of a transformer in the converter is connected across the input bus, while the secondary winding and switches are connected in series with the output bus, so that the output voltage is the sum of the input voltage and the secondary voltage of the converter. In the breadboard SCBBR, the input voltage applied to the primary winding is switched by use of metal oxide/semiconductor field-effect transistors (MOSFETs) in a full bridge circuit; the secondary winding is center-tapped, with two MOSFET switches and diode rectifiers connected in opposed series in each leg. The sets of opposed switches and rectifiers are what enable operation in either a boost or a buck mode. In the boost mode, input voltage and current, and the output voltage and current are all positive; that is, the secondary voltage is added to the input voltage and the net output voltage can be regulated at a value equal or greater than the input voltage. In the buck mode, input voltage is still positive and the current still flows in the same direction in the secondary, but the switches are controlled such that some power flows from the secondary to the primary. The voltage across the secondary and the current into the primary are reversed. The result is that the output voltage is lower than the input voltage, and some power is recirculated from the converter secondary back to the input. Quantitatively, the advantage of an SCBBR is a direct function of the regulation range required. If, for example, a regulation range of 20 percent is required for a 500-W supply, th it suffices to design the DC-to-DC converter in the SCBBR for a power rating of only 100 W. The switching loss and size are much smaller than those of a conventional regulator that must be rated for switching of all 500 W. The reduction in size and the increase in efficiency are not directly proportional to switched-power ratio of 5:1 because the additional switches contribute some conduction loss and the input and output filters must be larger than those typically required for a 100-W converter. Nevertheless, the power loss and the size can be much smaller than those of a 500-W converter.

Birchenough, Arthur G.↗
NASA NTRS2005

High-Efficiency Microwave Power Amplifier

A high-efficiency power amplifier that operates in the S band (frequencies of the order of a few gigahertz) utilizes transistors operating under class-D bias and excitation conditions. Class-D operation has been utilized at lower frequencies, but, until now, has not been exploited in the S band. Nominally, in class D operation, a transistor is switched rapidly between "on" and "off" states so that at any given instant, it sustains either high current or high voltage, but not both at the same time. In the ideal case of zero "on" resistance, infinite "off" resistance, zero inductance and capacitance, and perfect switching, the output signal would be a perfect square wave. Relative to the traditional classes A, B, and C of amplifier operation, class D offers the potential to achieve greater power efficiency. In addition, relative to class-A amplifiers, class-D amplifiers are less likely to go into oscillation. In order to design this amplifier, it was necessary to derive mathematical models of microwave power transistors for incorporation into a larger mathematical model for computational simulation of the operation of a class-D microwave amplifier. The design incorporates state-of-the-art switching techniques applicable only in the microwave frequency range. Another major novel feature is a transmission-line power splitter/combiner designed with the help of phasing techniques to enable an approximation of a square-wave signal (which is inherently a wideband signal) to propagate through what would, if designed in a more traditional manner, behave as a more severely band-limited device (see figure). The amplifier includes an input, a driver, and a final stage. Each stage contains a pair of GaAs-based field-effect transistors biased in class D. The input signal can range from -10 to +10 dBm into a 50-ohm load. The table summarizes the performances of the three stages

Sims, Williams H.↗
NASA NTRS2005

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

Zheng, Xinyu↗
NASA NTRS1994

Cryogenic GaAS JFETS

Gallium arsenide junction field-effect transistors (GaAS JFETS) are promising for deep cryogenic (<10k) readout electonics applications.

structure↗
DOE OSTI2025

Thermal Optimization and Experimental Demonstration of a Silicon Carbide, Half-Bridge Power Module

This paper describes modeling and experimental work to design and demonstrate a silicon carbide (SiC), single-side-cooled power module. Two SiC metal-oxide-semiconductor field-effect transistors (MOSFET) were used for each switch position and packaged on a metalized ceramic substrate. Thermal modeling was first conducted to optimize the module packaging to minimize junction-to-fluid thermal resistance and device temperature variations. This procedure identified the optimal device placement and baseplate thickness to maximize thermal performance. A heat exchanger - incorporating impinging jets of water-ethylene glycol - was designed to cool the module's baseplate to minimize thermal resistance and pumping power. The heat exchanger used relatively low fluid velocities (<1.5 m/s) to minimize erosion-corrosion effects and relatively large fluid channel sizes (>=1 mm) to prevent clogging. The power module concept was fabricated, and experiments were conducted to measure its thermal performance. Direct current was used to power the module devices, and junction temperatures were measured via device temperature-sensitive parameters. The experimental results were found to be in good agreement with model predictions (within 2%) and yielded junction-to-fluid thermal resistance values as low as about 15 mm2 K/W at relatively low pumping power values. The results demonstrate the improved performance associated with jet impingement cooling and represent an improvement over existing channel-flow-type cold plates, which can enable improvements to power density and reliability.

36 MATERIALS SCIENCE↗
DOE OSTI2024

The Critical Influence of Spin–Dry Technique on the Surface Passivation Quality of Crystalline Silicon Solar Cell Structures

This study examines the effects of spin-dry (SD) and N 2 blow-dry (ND) techniques on the quality and surface passivation performance of silicon oxide grown in ozone-dissolved deionized water. The SD method achieves greater oxide thickness uniformity, averaging 1.39 nm ± 4.17% across 49 points, compared to 1.68 nm ± 21.67% for the ND wafers. However, persistently poor passivation of ozonated oxide-grown wafers following the SD process is exhibited, with carrier lifetime, τ eff < 0.3 ms and saturation current density, J 0 (per side) ranging from 26 to 45 fA cm 2 . These findings are analyzed in the context of the fundamental phenomena involved in the drying processes of both techniques. Following this, an optimized spin-drying process is developed, resulting in improved τ eff and J 0 values of 1.4 ms and 5.6 fA cm –2 , respectively. Scanning electron microscopy further confirms that the oxide films dried with the enhanced SD technique are free of pinholes.

14 SOLAR ENERGY↗
DOE OSTI2025

Polarization-Controlled Structural Modulation in the Single Atomic Layer at the PbZr 0.2 Ti 0.8 O 3 /LaNiO 3 Interface

Conductivity modulation via ferroelectric polarization coupling with LaNiO 3 (LNO) is demonstrated at an epitaxial ferroelectric–LNO interface. Conductivity measurements, varying the thickness of the LNO channel, show that this phenomenon is confined to a few atomic layers at the interface. Combining in situ biasing and off-axis holography, we mapped out electrostatic potentials at the PbZr 0.2 Ti 0.8 O 3 (PZT)/LNO/SrTiO 3 (STO) heterostructure upon polarization switching. Using aberration-corrected STEM, the interfacial atomic structures were investigated for the two different PZT polarization states. Polarization in PZT induces a significant change in the in-plane O–Ni–O bond angles, with a 37° modulation in the topmost 1 or 2 LNO unit cells, driven by strain in the oxygen sublattice for the two opposite polarization directions in PZT. Both oxygen and cation sublattices exhibit strain responses exceeding 10% upon switching. This atomic-layer structural modulation highlights a mechanism for functional oxide heterostructure development, offering pathways for advancements in nonvolatile memory, sensors, and energy-efficient transistors.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2025

Theoretical perspective on phase stability and polarization switching in ferroelectric hafnia

Fluorite-based ferroelectric materials are revolutionizing the application space of polar semiconductors. These materials leverage robust polarization of extremely thin films, compatibility with the silicon chip processing, and decades of manufacturing experience to enable a new generation of ferroelectric memory devices. As a new paradigm for ferroelectrics, understanding of phase transitions and the switching mechanism in fluorites is essential both for advancing applications and for fundamental science. In this article, we outline the recent progress that has been made to understand the relative phase stability, phase transition and order parameter coupling, ferroelectric switching through unique nucleation and growth processes, and how defects affect these phases and processes. The main challenges, opportunities, and next steps for leveraging these materials for next-generation devices are reviewed.

Condensed Matter Physics↗
NASA NTRS2005

Beyond G-band : a 235 GHz InP MMIC amplifier

We present results on an InP monolithic millimeter- wave integrated circuit (MMIC) amplifier having 10-dB gain at 235 GHz. We designed this circuit and fabricated the chip in Northrop Grumman Space Technology's (NGST) 0.07- m InP high electron mobility transistor (HEMT) process. Using a WR3 (220-325 GHz) waveguide vector network analyzer system interfaced to waveguide wafer probes, we measured this chip on-wafer for -parameters. To our knowledge, this is the first time a WR3 waveguide on-wafer measurement system has been used to measure gain in a MMIC amplifier above 230 GHz.

high electron mobility transistors (HEMTs)↗