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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
NASA NTRS1982

Baseband processor development for the Advanced Communications Satellite Program

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

Moat, D.↗
NASA NTRS1982

A floating-point/multiple-precision processor for airborne applications

A compact input output (I/O) numerical processor capable of performing floating-point, multiple precision and other arithmetic functions at execution times which are at least 100 times faster than comparable software emulation is described. The I/O device is a microcomputer system containing a 16 bit microprocessor, a numerical coprocessor with eight 80 bit registers running at a 5 MHz clock rate, 18K random access memory (RAM) and 16K electrically programmable read only memory (EPROM). The processor acts as an intelligent slave to the host computer and can be programmed in high order languages such as FORTRAN and PL/M-86.

Yee, R.↗
NASA NTRS2012

System and method for cognitive processing for data fusion

A system and method for cognitive processing of sensor data. A processor array receiving analog sensor data and having programmable interconnects, multiplication weights, and filters provides for adaptive learning in real-time. A static random access memory contains the programmable data for the processor array and the stored data is modified to provide for adaptive learning.

Duong, Tuan A.↗
NASA NTRS1990

Line-drawing algorithms for parallel machines

The fact that conventional line-drawing algorithms, when applied directly on parallel machines, can lead to very inefficient codes is addressed. It is suggested that instead of modifying an existing algorithm for a parallel machine, a more efficient implementation can be produced by going back to the invariants in the definition. Popular line-drawing algorithms are compared with two alternatives; distance to a line (a point is on the line if sufficiently close to it) and intersection with a line (a point on the line if an intersection point). For massively parallel single-instruction-multiple-data (SIMD) machines (with thousands of processors and up), the alternatives provide viable line-drawing algorithms. Because of the pixel-per-processor mapping, their performance is independent of the line length and orientation.

Pang, Alex T.↗
NASA NTRS1991

An electronic pan/tilt/zoom camera system

A camera system for omnidirectional image viewing applications that provides pan, tilt, zoom, and rotational orientation within a hemispherical field of view (FOV) using no moving parts was developed. The imaging device is based on the effect that from a fisheye lens, which produces a circular image of an entire hemispherical FOV, can be mathematically corrected using high speed electronic circuitry. An incoming fisheye image from any image acquisition source is captured in memory of the device, a transformation is performed for the viewing region of interest and viewing direction, and a corrected image is output as a video image signal for viewing, recording, or analysis. As a result, this device can accomplish the functions of pan, tilt, rotation, and zoom throughout a hemispherical FOV without the need for any mechanical mechanisms. A programmable transformation processor provides flexible control over viewing situations. Multiple images, each with different image magnifications and pan tilt rotation parameters, can be obtained from a single camera. The image transformation device can provide corrected images at frame rates compatible with RS-170 standard video equipment.

Zimmermann, Steve↗
NASA NTRS2011

Ion Exchange Technology Development in Support of the Urine Processor Assembly Precipitation Prevention Project for the International Space Station

In support of the Urine Processor Assembly Precipitation Prevention Project (UPA PPP), multiple technologies were explored to prevent CaSO4 dot 2H2O (gypsum) precipitation during the on-orbit distillation process. Gypsum precipitation currently limits the water recovery rate onboard the International Space Station (ISS) to 70% versus the planned 85% target water recovery rate. Due to its advanced performance in removing calcium cations in pretreated augmented urine (PTAU), ion exchange was selected as one of the technologies for further development by the PPP team. A total of 12 ion exchange resins were evaluated in various equilibrium and dynamic column tests with solutions of dissolved gypsum, urine ersatz, PTAU, and PTAU brine at 85% water recovery. While initial evaluations indicated that the Purolite SST60 resin had the highest calcium capacity in PTAU (0.30 meq/mL average), later tests showed that the Dowex G26 and Amberlite FPC12H resins had the highest capacity (0.5 meq/mL average). Further dynamic column testing proved that G26 performance is +/- 10% of that value at flow rates of 0.45 and 0.79 Lph under continuous flow, and 10.45 Lph under pulsed flow. Testing at the Marshall Spaceflight Center (MSFC) integrates the ion exchange technology with a UPA ground article under flight-like pulsed flow conditions with PTAU. To date, no gypsum precipitation has taken place in any of the initial evaluations.

Mitchell, Julie L.↗
NASA NTRS2012

Ion Exchange Technology Development in Support of the Urine Processor Assembly Precipitation Prevention Project for the International Space Station

In support of the Urine Processor Assembly Precipitation Prevention Project (UPA PPP), multiple technologies were explored to prevent CaSO4 2H2O (gypsum) precipitation during the on-orbit distillation process. Gypsum precipitation currently limits the water recovery rate onboard the International Space Station (ISS) to 70% versus the planned 85% target water recovery rate. Due to its ability to remove calcium cations in pretreated augmented urine (PTAU), ion exchange was selected as one of the technologies for further development by the PPP team. A total of 13 ion exchange resins were evaluated in various equilibrium and dynamic column tests with solutions of dissolved gypsum, urine ersatz, PTAU, and PTAU brine at 85% water recovery. While initial evaluations indicated that the Purolite SST60 resin had the highest calcium capacity in PTAU (0.30 meq/mL average), later tests showed that the Dowex G26 and Amberlite FPC12H resins had the highest capacity (0.5 meq/mL average). Testing at the Marshall Spaceflight Center (MSFC) integrates the ion exchange technology with a UPA ground article under flight-like pulsed flow conditions with PTAU. To date, no gypsum precipitation has taken place in any of the initial evaluations.

Mitchell, Julie L.↗
NASA NTRS1994

An implementation of a tree code on a SIMD, parallel computer

We describe a fast tree algorithm for gravitational N-body simulation on SIMD parallel computers. The tree construction uses fast, parallel sorts. The sorted lists are recursively divided along their x, y and z coordinates. This data structure is a completely balanced tree (i.e., each particle is paired with exactly one other particle) and maintains good spatial locality. An implementation of this tree-building algorithm on a 16k processor Maspar MP-1 performs well and constitutes only a small fraction (approximately 15%) of the entire cycle of finding the accelerations. Each node in the tree is treated as a monopole. The tree search and the summation of accelerations also perform well. During the tree search, node data that is needed from another processor is simply fetched. Roughly 55% of the tree search time is spent in communications between processors. We apply the code to two problems of astrophysical interest. The first is a simulation of the close passage of two gravitationally, interacting, disk galaxies using 65,636 particles. We also simulate the formation of structure in an expanding, model universe using 1,048,576 particles. Our code attains speeds comparable to one head of a Cray Y-MP, so single instruction, multiple data (SIMD) type computers can be used for these simulations. The cost/performance ratio for SIMD machines like the Maspar MP-1 make them an extremely attractive alternative to either vector processors or large multiple instruction, multiple data (MIMD) type parallel computers. With further optimizations (e.g., more careful load balancing), speeds in excess of today's vector processing computers should be possible.

Olson, Kevin M.↗
NASA NTRS1975

A multiple thruster array for 30-cm thrusters

A 3.0 m diameter chamber of the 7.6 m diameter by 21.4 m long vacuum tank was modified to permit testing of an array of up to six 30-cm thrusters with a variety of laboratory and thermal vacuum breadboard power systems. A primary objective of the Multiple Thruster Array (MTA) program is to assess the impact of multiple thruster operation on individual thruster and power processor requirements. The areas of thruster startup, steady-state operation, throttling, high voltage recycle, thrust vectoring, and shutdown are of special concern. The results of initial tests are reported.

Rawlin, V. K.↗
NASA NTRS1975

A multiple thruster array for 30-cm thrusters

The 3.0-m diameter chamber of the 7.6-m diameter by 21.4-m long vacuum tank at NASA LeRC was modified to permit testing of an array of up to six 30-cm thrusters with a variety of laboratory and thermal vacuum bread-board power systems. A primary objective of the Multiple Thruster Array (MTA) program is to assess the impact of multiple thruster operation on individual thruster and power processor requirements. The areas of thruster startup, steady-state operation, throttling, high voltage recycle, thrust vectoring, and shutdown are of special concern. The results of initial tests are reported.

Rawlin, V. K.↗
NASA NTRS1989

A computational fluid dynamics algorithm on a massively parallel computer

The implementation and performance of a finite-difference algorithm for the compressible Navier-Stokes equations in two or three dimensions on the Connection Machine are described. This machine is a single-instruction multiple-data machine with up to 65536 physical processors. The implicit portion of the algorithm is of particular interest. Running times and megadrop rates are given for two- and three-dimensional problems. Included are comparisons with the standard codes on a Cray X-MP/48.

Jespersen, Dennis C.↗
NASA NTRS1999

Development and Performance of the ACTS High Speed VSAT

The Advanced Communication Technology Satellite (ACTS), developed by the U.S. National Aeronautics and Space Administration (NASA) has demonstrated the breakthrough technologies of Ka-band, spot beam antennas, and on-board processing. These technologies have enabled the development of very small aperture terminals (VSAT) and ultra-small aperture terminals (USAT) which have capabilities greater than were previously possible with conventional satellite technologies. However, the ACTS baseband processor (BBP) is designed using a time division multiple access (TDMA) scheme, which requires each earth station using the BBP to transmit data at a burst rate which is much higher than the user throughput data rate. This tends to mitigate the advantage of the new technologies by requiring a larger earth station antenna and/or a higher-powered uplink amplifier than would be necessary for a continuous transmission at the user data rate. Conversely, the user data rate is much less than the rate that can be supported by the antenna size and amplifier. For example, the ACTS TI VSAT operates at a burst rate of 27.5 Mbps, but the maximum user data rate is 1.792 Mbps. The throughput efficiency is slightly more than 6.5%. For an operational network, this level of overhead will greatly increase the cost of the user earth stations, and that increased cost must be repeated thousands of times, which may ultimately reduce the market for such a system. The ACTS High Speed VSAT (HS VSAT) is an effort to experimentally demonstrate the maximum user throughput data rate which can be achieved using the technologies developed and implemented on ACTS. Specifically, this was done by operating the system uplinks as frequency division multiple access (FDMA), essentially assigning all available TDMA time slots to a single user on each of two uplink frequencies. Preliminary results show that using a 1.2-m antenna in this mode, the HS VSAT can achieve between 22 and 24 Mbps out of the 27.5 Mbps burst rate, for a throughput efficiency of 80-88%. This paper describes the modifications made to the TI VSAT to enable it to operate at high speed, including hardware considerations, interface modifications, and software modifications. In addition, it describes the results of NASA HS VSAT experiments, continuing work on an improved user interface, and plans for future experiments.

Quintana, J.↗
NASA NTRS1993

Application of compiler-assisted multiple instruction rollback recovery to speculative execution

Speculative execution is a method to increase instruction level parallelism which can be exploited by both super-scalar and VLIW architectures. The key to a successful general speculation strategy is a repair mechanism to handle mispredicted branches and accurate reporting of exceptions for speculated instructions. Multiple instruction rollback is a technique developed for recovery from transient processor failure. Many of the difficulties encountered during recovery from branch misprediction or from instruction re-execution due to exception in a speculative execution architecture are similar to those encountered during multiple instruction rollback. The applicability of a recently developed compiler-assisted multiple instruction rollback scheme to aid in speculative execution repair is investigated. Extensions to the compiler-assisted scheme to support branch and exception repair are presented along with performance measurements across ten application programs.

Alewine, N. J.↗
NASA NTRS1993

Application of compiler-assisted multiple instruction rollback recovery to speculative execution

Speculative execution is a method to increase instruction level parallelism which can be exploited by both super-scalar and VLIW architectures. The key to a successful general speculation strategy is a repair mechanism to handle mispredicted branches and accurate reporting of exceptions for speculated instructions. Multiple instruction rollback is a technique developed for recovery from transient processor failure. Many of the difficulties encountered during recovery from branch misprediction or from instruction re-execution due to exception in a speculative execution architecture are similar to those encountered during multiple instruction rollback. The applicability of a recently developed compiler-assisted multiple instruction rollback scheme to aid in speculative execution repair is investigated. Extensions to the compiler-assisted scheme to support branch and exception repair are presented along with performance measurements across ten application programs.

Alewine, N. J.↗
NASA NTRS1989

Parallel eigenanalysis of finite element models in a completely connected architecture

A parallel algorithm is presented for the solution of the generalized eigenproblem in linear elastic finite element analysis, (K)(phi) = (M)(phi)(omega), where (K) and (M) are of order N, and (omega) is order of q. The concurrent solution of the eigenproblem is based on the multifrontal/modified subspace method and is achieved in a completely connected parallel architecture in which each processor is allowed to communicate with all other processors. The algorithm was successfully implemented on a tightly coupled multiple-instruction multiple-data parallel processing machine, Cray X-MP. A finite element model is divided into m domains each of which is assumed to process n elements. Each domain is then assigned to a processor or to a logical processor (task) if the number of domains exceeds the number of physical processors. The macrotasking library routines are used in mapping each domain to a user task. Computational speed-up and efficiency are used to determine the effectiveness of the algorithm. The effect of the number of domains, the number of degrees-of-freedom located along the global fronts and the dimension of the subspace on the performance of the algorithm are investigated. A parallel finite element dynamic analysis program, p-feda, is documented and the performance of its subroutines in parallel environment is analyzed.

Akl, F. A.↗
NASA NTRS2012

Design and Implementation of the PALM-3000 Real-Time Control System

This paper reflects, from a computational perspective, on the experience gathered in designing and implementing realtime control of the PALM-3000 adaptive optics system currently in operation at the Palomar Observatory. We review the algorithms that serve as functional requirements driving the architecture developed, and describe key design issues and solutions that contributed to the system's low compute-latency. Additionally, we describe an implementation of dense matrix-vector-multiplication for wavefront reconstruction that exceeds 95% of the maximum sustained achievable bandwidth on NVIDIA Geforce 8800GTX GPU.

PALM-3000↗
NASA NTRS1989

Eigensolution of finite element problems in a completely connected parallel architecture

A parallel algorithm for the solution of the generalized eigenproblem in linear elastic finite element analysis, (K)(phi)=(M)(phi)(omega), where (K) and (M) are of order N, and (omega) is of order q is presented. The parallel algorithm is based on a completely connected parallel architecture in which each processor is allowed to communicate with all other processors. The algorithm has been successfully implemented on a tightly coupled multiple-instruction-multiple-data (MIMD) parallel processing computer, Cray X-MP. A finite element model is divided into m domains each of which is assumed to process n elements. Each domain is then assigned to a processor, or to a logical processor (task) if the number of domains exceeds the number of physical processors. The macro-tasking library routines are used in mapping each domain to a user task. Computational speed-up and efficiency are used to determine the effectiveness of the algorithm. The effect of the number of domains, the number of degrees-of-freedom located along the global fronts and the dimension of the subspace on the performance of the algorithm are investigated. For a 64-element rectangular plate, speed-ups of 1.86, 3.13, 3.18 and 3.61 are achieved on two, four, six and eight processors, respectively.

Akl, Fred A.↗