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At least 199 records · Page 11

Silicon Nanowire Growth at Chosen Positions and Orientations

It is now possible to grow silicon nanowires at chosen positions and orientations by a method that involves a combination of standard microfabrication processes. Because their positions and orientations can be chosen with unprecedented precision, the nanowires can be utilized as integral parts of individually electronically addressable devices in dense arrays. Nanowires made from silicon and perhaps other semiconductors hold substantial promise for integration into highly miniaturized sensors, field-effect transistors, optoelectronic devices, and other electronic devices. Like bulk semiconductors, inorganic semiconducting nanowires are characterized by electronic energy bandgaps that render them suitable as means of modulating or controlling electronic signals through electrostatic gating, in response to incident light, or in response to molecules of interest close to their surfaces. There is now potential for fabricating arrays of uniform, individually electronically addressable nanowires tailored to specific applications. The method involves formation of metal catalytic particles at the desired positions on a substrate, followed by heating the substrate in the presence of silane gas. The figure illustrates an example in which a substrate includes a silicon dioxide surface layer that has been etched into an array of pillars and the catalytic (in this case, gold) particles have been placed on the right-facing sides of the pillars. The catalytic thermal decomposition of the silane to silicon and hydrogen causes silicon columns (the desired nanowires) to grow outward from the originally catalyzed spots on the substrate, carrying the catalytic particles at their tips. Thus, the position and orientation of each silicon nanowire is determined by the position of its originally catalyzed spot on the substrate surface, and the orientation of the nanowire is perpendicular to the substrate surface at the originally catalyzed spot.

Getty, Stephanie A.↗

High Temperature Devices for Aerospace Applications

This presentation will overview important new capabilities and benefits that next-generation higher temperature electronics promise for a variety of aerospace systems and missions. Initial aerospace infusions of higher temperature electronics to be discussed include jet engines and the prolonged robotic exploration of the Venus surface. Complete redesign of systems compared to prior conventional electronics practices would yield the most revolutionary benefits. However, the inherent higher risk and expense associated with new technology adoption will likely drive a more evolutionary technology infusion process, especially since flight qualification demands large safety margins and testing that ensures reliable operation for far longer than actual mission duration. SiC pn-junction based devices are inherently capable of the most durable operation at the highest application temperatures compared other transistor technologies, but such integrated circuits (ICs) will never achieve integration levels near today’s silicon ICs. Extreme temperature high-power devices will also be de-rated compared to room-temperature performance. While the high temperature market will always be small compared to the conventional temperature mass-market, compatibility and leveraging of existing foundry manufacturing is vital to the establishment of a sustainable high temperature electronics ecosystem sufficient to significantly improve aerospace systems.

High Temperature↗

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

Krasowski, Michael J.↗

The light-sensitive MNOS memory transistor.

The behavior theory of the light-sensitive MNOS memory transistor is developed and supported by presented experimental evidence. It is shown that the nitride, oxide, and silicon space-charge current-field relationships necessary for comparison of theory and experiment can be obtained from steady-state current-voltage measurements on the MNOS device.

Sewell, F. A., Jr.↗

Studies of silicon p-n junction solar cells

To provide theoretical support for investigating different ways to obtain high open-circuit voltages in p-n junction silicon solar cells, an analytical treatment of heavily doped transparent-emitter devices is presented that includes the effects of bandgap narrowing, Fermi-Dirac statistics, a doping concentration gradient, and a finite surface recombination velocity at the emitter surface. Topics covered include: (1) experimental determination of bandgap narrowing in the emitter of silicon p-n junction devices; (2) heavily doped transparent regions in junction solar cells, diodes, and transistors; (3) high-low-emitter solar cell; (4) determination of lifetimes and recombination currents in p-n junction solar cells; (5) MOS and oxide-charged-induced BSF solar cells; and (6) design of high efficiency solar cells for space and terrestrial applications.

Neugroschel, A.↗

Commutating Permanent-Magnet Motors At Low Speed

Circuit provides forced commutation during starting. Forced commutation circuit diverts current from inverter SCR's and turns SCR's off during commutation intervals. Silicon controlled rectifier in circuit unnecessary when switch S10 replaced by high-current, high-voltage transistor. At present, high-current, low-voltage device must suffice.

Dolland, C.↗

Material growth and characterization for solid state devices

During this period InGaAs and InGaAsP were grown on (100)InP by liquid phase electroepitaxy (LPEE). Results of the epitaxial growth of InGaAs on sputtered quartz masked substrates are presented. The resulting surface morphology can be related to the current density distribution near the edges of a masked pattern. The quaternary InGaAs was grown with compositions corresponding to 1.3 micron and 1.5 micron emission wavelengths. Growth rates were found to be linearly dependent upon current density, and a strong dependence upon composition was noted. These compositions lie in the miscibility gap region of the alloy phase diagram at the 645 C growth temperature. Growths were performed at 685 C to avoid the miscibility gap. Epilayers were characterized by photoluminescence, X-ray diffraction, secondary ion mass spectrometry, and Hall effect measurements. Aluminum oxide was deposited on silicon and InGaAs substrates for the characterization of this material as an insulator in a field effect transistor structure. It was determined that the results did not warrant further work with the deposition from an aluminum isopropoxide source. A metallographic vapor phase epitaxy system installation is nearing completion for use in hybrid III-V semiconductor epilayer growths.

Collis, Ward J.↗

A Two-Dimensional, Semiconducting Bolometer Array for HAWC

The Stratospheric Observatory For Infrared Astronomy's (SOFIA's) High resolution Airborne Wideband Camera (HAWC) will use an ion-implanted silicon bolometer array developed at NASA s Goddard Space Flight Center (GSFC). The GSFC Pop-Up Detectors (PUDs) use a unique folding technique to enable a 12 x 32 element closepacked array of bolometers with a filling factor greater than 95%. The HAWC detector uses a resistive metal film on silicon to provide frequency independent, approx. 50% absorption over the 40 - 300 micron band. The silicon bolometers are manufactured in 32-element rows within silicon frames using Micro Electro Mechanical Systems (MEMS) silicon etching techniques. The frames are then cut, "folded", and glued onto a metallized, ceramic, thermal bus "bar". Optical alignment using micrometer jigs ensures their uniformity and correct placement. The rows are then stacked side-by-side to create the final 12 x 32 element array. A kinematic Kevlar suspension system isolates the 200 mK bolometer cold stage from the rest of the 4K detector housing. GSFC - developed silicon bridge chips make electrical connection to the bolometers, while maintaining thermal isolation. The Junction Field Effect Transistor (JFET) preamplifiers for all the signal channels operate at 120 K, yet they are electrically connected and located in close proximity to the bolometers. The JFET module design provides sufficient thermal isolation and heat sinking for these, so that their heat is not detected by the bolometers. Preliminary engineering results from the flight detector dark test run are expected to be available in July 2004. This paper describes the array assembly and mechanical and thermal design of the HAWC detector and the JFET module.

Voellmer, George M.↗

Heavy doping effects in high efficiency silicon solar cells

The use of a (silicon)/(heavily doped polysilicon)/(metal) structure to replace the conventional high-low junction (or back-surface-field, BSF) structure of silicon solar cells was examined. The results of an experimental study designed to explore both qualitatively and quantitatively the mechanism of the improved current gain in bipolar transistors with polysilicon emitter contact are presented. A reciprocity theorem is presented that relates the short circuit current of a device, induced by a carrier generation source, to the minority carrier Fermi level in the dark. A method for accurate measurement of minority-carrier diffusion coefficients in silicon is described.

Lindholm, F. A.↗

Growing Cobalt Silicide Columns In Silicon

Codeposition by molecular-beam epitaxy yields variety of structures. Proposed fabrication process produces three-dimensional nanometer-sized structures on silicon wafers. Enables control of dimensions of metal and semiconductor epitaxial layers in three dimensions instead of usual single dimension (perpendicular to the plane of the substrate). Process used to make arrays of highly efficient infrared sensors, high-speed transistors, and quantum wires. For fabrication of electronic devices, both shapes and locations of columns controlled. One possible technique for doing this electron-beam lithography, see "Making Submicron CoSi2 Structures on Silicon Substrates" (NPO-17736).

Fathauer, Obert W.↗

High Mobility SiGe/Si Transistor Structures on Sapphire Substrates Using Ion Implantation

High mobility n-type SiGe/Si transistor structures have been fabricated on sapphire substrates by ion implanting phosphorus ions into strained 100 Angstrom thick silicon channels for the first time. The strained Si channels were sandwiched between Si(sub 0.7)Ge(sub 0.3) layers, which, in turn, were deposited on Si(sub 0.7)Ge(sub 0.3) virtual substrates and graded SiGe buffer layers. After the molecular beam epitaxy (MBE) film growth process was completed, ion thick silicon channels implantation and post-annealing were used to introduce donors. The phosphorous ions were preferentially located in the Si channel at a peak concentration of approximately 1x10(exp 18)/cu cm. Room temperature electron mobilities exceeding 750 sq cm/V-sec at carrier densities of 1x10(exp 12)/sq cm were measured. Electron concentration appears to be the key factor that determines mobility, with the highest mobility observed for electron densities in the 1 - 2x10(exp 12)/sq cm range.

Alterovitz, S. A.↗

Stacked-Gate FET's For Analog Memory Elements

Three-terminal, double-stacked-gate field-effect transistor (FET), developed as analog memory element. Particularly suited for use as synapse with variable connection strength in electronic neural network. Provides programmable, nonvolatile resistive connection, somewhat in manner of porous-gate FET described in "Porous-Floating-Gate Field-Effect Transistor" (NPO-17532). Resembles commercial erasable programmable read-only memory (EPROM) device, except for thickness of layers of silicon dioxide electrically isolating gates. Either p-channel or n-channel device.

Thakoor, Anilkumar P.↗

Voltage-offset reduction in data transmitters

Current source, which consists of inductor and two silicon diodes, is used to reduce output voltage offset and to make circuit less sensitive to conductance differences in output transistors.

Theall, C. E.↗

Measurement of minority carrier transport parameters in heavily doped n-type silicon

Measurement of minority transport parameters in heavily doped silicon is covered. The basic transport equations were used to define two independent parameters. Use of special vertical and lateral transistor test devices permitted the measurement of both parameters. Prior studies were normalized to show excellent agreement over the heavy doping region.

Delalamo, J.↗

Transport Modeling for Metallic Electrode: Semiconducting Nanotube Systems

Recently, current-voltage (I-V) characteristics have been reported by Collins et al. for a system with a scanning tunneling microscope (STM) tip and a carbon nanotube. The STM tip was driven forward into a film of many entangled nanotubes on a substrate, and then was retracted, so that one of nanotubes bridged the STM and the film. I-V characteristics had two different patterns for different heights. One showed large dI/ dV with V greater than 0, small dI/dV with V less than 0, and I = 0 near V = 0 (type-I), while the other showed rectification, i.e., I does not equal 0 only with V less than 0 (type-II), with the tip grounded. We propose a physical mechanism to explain the observed I-V patterns. We consider that the observed characteristics strongly reflected the nature of the tip (metal) - nanotube (semiconductor) contact. The other end of the nanotube was entangled well in the film, and simply provided a good Ohmic contact. We will argue that there are two different contact modes: vacuum gap and touching modes, depending on the presence or absence of a tiny vacuum gap d approx. 0.1 - 0.2 nm at the junction. These modes may be related to physisorption and chemisorption, respectively. Once admitting their existence, it is naturally shown that I-V characteristics are type-I in the vacuum gap mode, and type-II in the touching mode. We argue that the nanotube had to be an n-type semiconductor judging from the I-V characteristics, contrary to often observed p-type in the transistor applications, where p-type is probably due to the oxidation in air or the trapped charges in the silicon dioxide. Additional information is contained in the original extended abstract.

Yamada, Toshishige↗

Photovoltaic Hydrogen Sensor

Photovoltaic device senses hydrogen developed to test degradation of diodes with platinum flash gates on backs. Sensing element is p/n junction rather than conventional Schottky barrier or metal oxide/silicon field-effect transistor. Hydrogen-indicating electrical signal modulated optically rather than electrically. Layered structure of hydrogen detector and principle of operation resemble silicon solar photovoltaic cell. Hydrogen detector responds to hydrogen in atmosphere within minutes and recovers quickly when hydrogen removed.

Daud, Taher↗