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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 199 records · Page 11

Advanced combined iodine dispenser and detector

A total weight of 1.23 kg (2.7 lb), a total volume of 1213 cu m (74 cu in), and an average power consumption of 5.5W was achieved in the advanced combined iodine dispenser/detector by integrating the detector with the iodine source, arranging all iodinator components within a compact package and lowering the parasitic power to the detector and electronics circuits. These achievements surpassed the design goals of 1.36 kg (3.0 lb), 1671 cu m (102 cu in) and 8W. The reliability and maintainability were improved by reducing the detector lamp power, using an interchangeable lamp concept, making the electronic circuit boards easily accessible, providing redundant water seals and improving the accessibility to the iodine accumulator for refilling. The system was designed to iodinate (to 5 ppm iodine) the fuel cell water generated during 27 seven-day orbiter missions (equivalent to 18,500 kg (40,700 lb) of water) before the unit must be recharged with iodine crystals.

Lantz, J. B.↗

Development and verification of NASA Standard Initiator-2 (NSI-2)

The results of verification testing under NASA Contract NAS9-17249 are summarized in this Final Report. An Appendix is published separately. The report contains a brief discussion of design elements, test results, and a discussion of the latter. The contract was awarded for development and demonstration of design modifications to the NASA Standard Initiator-1 (NSI-1), resulting in the development of NSI-2. The intent of the project was to develop and prove the following design features: (1) Protection from premature initiation due to electrostatic potential by means other than a spark gap; (2) Development of an integral insulated charge cup for use with a zirconium/potassium perchlorate type mixture; (3) Improved cost and reliability figures by the use of a deposited ridge; and (4) Elimination of dudding as a result of the pyrotechnic shock effect, the movement of the primer composition away from the bridge circuit.

Corbin-Roberts, Linda↗

Development and verification of NASA Standard Initiator-2 (NSI-2): Appendix

This is the Appendix to the Final Report on the results of verification testing on NASA Contract NAS9-17249. The test results are presented graphically in the Appendix. The Final Report is a brief discussion of design elements, test results, and a discussion of the latter. The contract was awarded for development and demonstration of design modifications to the NASA Standard Initiator-1 (NSI-1), resulting in the development of NSI-2. The intent of the project was to develop and prove the following design features: (1) Protection from premature detonation due to electrostatic potential by means other than a spark gap; (2) Development of an integral insulated charge cup for use with a zirconium/potassium perchlorate type mixture; (3) Improved cost and reliability figures by the use of a deposited bridge; and (4) Elimination of dudding as a result of the pyrotechnic shock effect, the movement of the primer composition away from the bridge circuit.

Source record↗

Design, processing, and testing of LSI arrays for space station

The applicability of a particular process for the fabrication of large scale integrated circuits is described. Test arrays were designed, built, and tested, and then utilized. A set of optimum dimensions for LSI arrays was generated. The arrays were applied to yield improvement through process innovation, and additional applications were suggested in the areas of yield prediction, yield modeling, and process reliability.

Ipri, A. C.↗

Evaluation of advanced microelectronic fluxless solder-bump contacts for hybrid microcircuits

Technology for interconnecting monolithic integrated circuit chips with other components is investigated. The advantages and disadvantages of the current flip-chip approach as compared to other interconnection methods are outlined. A fluxless solder-bump contact technology is evaluated. Multiple solder-bump contacts were formed on silicon integrated circuit chips. The solder-bumps, comprised of a rigid nickel under layer and a compliant solder overlayer, were electroformed onto gold device pads with the aid of thick dry film photomasks. Different solder alloys and the use of conductive epoxy for bonding were explored. Fluxless solder-bump bond quality and reliability were evaluated by measuring the effects of centrifuge, thermal cycling, and high temperature storage on bond visual characteristics, bond electrical continuity, and bond shear tests. The applicability and suitability of this technology for hybrid microelectronic packaging is discussed.

Mandal, R. P.↗

An application specific integrated circuit based multi-anode microchannel array readout system

Size reduction of two new multi-anode microchannel array (MAMA) readout systems is described. The systems are based on two analog and one digital application specific integrated circuits (ASICs). The new readout systems reduce volume over previous discrete designs by 80 percent while improving electrical performance on virtually every significant parameter. Emphasis is made on the packaging used to achieve the volume reduction. Surface mount technology (SMT) is combined with modular construction for the analog portion of the readout. SMT reliability concerns and the board area impact of MIL SPEC SMT components is addressed. Package selection for the analog ASIC is discussed. Future sytems will require even denser packaging and the volume reduction progression is shown.

Smeins, Larry G.↗

Design Consideration on the ACTS T1-VSAT

The Advanced Communications Technology Satellite (ACTS) was developed by NASA as an experimental platform to demonstrate to industry the high risk technologies need for the next generation of communication satellites. The ACTS contains many state-of-the-art technologies including time division multiple accessing, adaptive error correction coding, multiple electronically steerable hopping beam antennas, spectrally efficient SMSK modulation, demand assignment multiple access protocol and on-board baseband circuit switching. An integral part of this testbed is the ACTS T1-very small aperture terminal (VSAT). The requirements imposed on the T1-VSAT demanded numerous design tradeoffs; balancing risk, cost, and implementation. Some of these considerations include: the method used for determining link quality, the development of a low cost and reliable Ka-band high power amplifier, the integration and testing environment for use in development and production and the low cost signal processing solution to high rate burst data. This paper discusses the tradeoffs considered in the selected implementation and the results obtained over the past two years of operation. Recommendations for improvements are also included.

Lilley, Richard D.↗

Pulsed Laser System to Simulate Effects of Cosmic Rays in Semiconductor Devices

Spaceflight system electronic devices must survive a wide range of radiation environments with various particle types including energetic protons, electrons, gamma rays, x-rays, and heavy ions. High-energy charged particles such as heavy ions can pass straight through a semiconductor material and interact with a charge-sensitive region, generating a significant amount of charge (electron-hole pairs) along their tracks. These excess charges can damage the device, and the response can range from temporary perturbations to permanent changes in the state or performance. These phenomena are called single event effects (SEE). Before application in flight systems, electronic parts need to be qualified and tested for performance and radiation sensitivity. Typically, their susceptibility to SEE is tested by exposure to an ion beam from a particle accelerator. At such facilities, the device under test (DUT) is irradiated with large beams so there is no fine resolution to investigate particular regions of sensitivity on the parts. While it is the most reliable approach for radiation qualification, these evaluations are time consuming and costly. There is always a need for new cost-efficient strategies to complement accelerator testing: pulsed lasers provide such a solution. Pulsed laser light can be utilized to simulate heavy ion effects with the advantage of being able to localize the sensitive region of an integrated circuit. Generally, a focused laser beam of approximately picosecond pulse duration is used to generate carrier density in the semiconductor device. During irradiation, the laser pulse is absorbed by the electronic medium with a wavelength selected accordingly by the user, and the laser energy can ionize and simulate SEE as would occur in space. With a tightly focused near infrared (NIR) laser beam, the beam waist of about a micrometer can be achieved, and additional scanning techniques are able to yield submicron resolution. This feature allows mapping of all of the sensitive regions of the studied device with fine resolution, unlike heavy ion experiments. The problematic regions can be precisely identified, and it provides a considerable amount of information about the circuit. In addition, the system allows flexibility for testing the device in different configurations in situ.

Aveline, David C.↗

Vanguard Satellite Separation Mechanisms

Early in the Vanguard program it became apparent that a thoroughly reliable means of separating the satellite packages from the third-stage rocket would be required. A completely self -contained standard mechanism was developed with redundant firing circuits for use on both test vehicles and satellite-launching vehicles. A change in the experimental objectives of the test-vehicle payload units necessitated modification of some of the standard separation mechanisms. A strap, pull-pin, girth-ring separation device was developed which employed the basic actuation of the standard mechanisms. Evidence of residual burning of the third stage made it necessary to delay separation longer than the time designed into the long-delay separation device. The standard separation mechanism was modified and integrated with the satellite command receiver system so that a ground command after third-stage burnout would cause separation. Flight performance of the various separation mechanisms proved their reliability; they performed without failure in all Vanguard launchings.

Baumann, Robert C.↗

Product Reliability Trends, Derating Considerations and Failure Mechanisms with Scaled CMOS

As microelectronics is scaled into the deep sub-micron regime, space and aerospace users of advanced technology CMOS are reassessing how scaling effects impact long-term product reliability. The effects of electromigration (EM), time-dependent-dielectric-breakdown (TDDB) and hot carrier degradation (HCI and NBTI) wearout mechanisms on scaled technologies and product reliability are investigated, accelerated stress testing across several technology nodes is performed, and FA is conducted to confirm the failure mechanism(s).

CMOS integrated circuits↗

Cost effective development of a Shuttle-based astronomical instrument control system

The high level language FORTH is used for the electronic control of the Space Shuttle-based Ultraviolet Imaging Telescope, in a flight computer system which minimizes costs. The greater part of the breadboard version of the flight computer is assembled from commercially available components, reducing novel circuit design features and permitting simultaneous development of both hardware and software. The commercial boards are then refabricated on aluminum core heat conducting stock, using high reliability parts to produce the flight versions of the system. The system's ground support equipment employs a MINC-25 minicomputer which performs such functions as flight computer software development, PROM programming, test and integration support, and flight operations support. The implementation of these concepts in flight computer telescope controls is described.

Parise, R. A.↗

A DRAM compiler algorithm for high performance VLSI embedded memories

In many applications, the limited density of the embedded SRAM does not allow integrating the memory on the same chip with other logic and functional blocks. In such cases, the embedded DRAM provides the optimum combination of very high density, low power, and high performance. For ASIC's to take full advantage of this design strategy, an efficient and highly reliable DRAM compiler must be used. The embedded DRAM architecture, cell, and peripheral circuit design considerations and the algorithm of a high performance memory compiler are presented .

Eldin, A. G.↗

Configurable Multi-Purpose Processor

Advancements in technology have allowed the miniaturization of systems used in aerospace vehicles. This technology is driven by the need for next-generation systems that provide reliable, responsive, and cost-effective range operations while providing increased capabilities such as simultaneous mission support, increased launch trajectories, improved launch, and landing opportunities, etc. Leveraging the newest technologies, the command and telemetry processor (CTP) concept provides for a compact, flexible, and integrated solution for flight command and telemetry systems and range systems. The CTP is a relatively small circuit board that serves as a processing platform for high dynamic, high vibration environments. The CTP can be reconfigured and reprogrammed, allowing it to be adapted for many different applications. The design is centered around a configurable field-programmable gate array (FPGA) device that contains numerous logic cells that can be used to implement traditional integrated circuits. The FPGA contains two PowerPC processors running the Vx-Works real-time operating system and are used to execute software programs specific to each application. The CTP was designed and developed specifically to provide telemetry functions; namely, the command processing, telemetry processing, and GPS metric tracking of a flight vehicle. However, it can be used as a general-purpose processor board to perform numerous functions implemented in either hardware or software using the FPGA s processors and/or logic cells. Functionally, the CTP was designed for range safety applications where it would ultimately become part of a vehicle s flight termination system. Consequently, the major functions of the CTP are to perform the forward link command processing, GPS metric tracking, return link telemetry data processing, error detection and correction, data encryption/ decryption, and initiate flight termination action commands. Also, the CTP had to be designed to survive and operate in a launch environment. Additionally, the CTP was designed to interface with the WFF (Wallops Flight Facility) custom-designed transceiver board which is used in the Low Cost TDRSS Transceiver (LCT2) also developed by WFF. The LCT2 s transceiver board demodulates commands received from the ground via the forward link and sends them to the CTP, where they are processed. The CTP inputs and processes data from the inertial measurement unit (IMU) and the GPS receiver board, generates status data, and then sends the data to the transceiver board where it is modulated and sent to the ground via the return link. Overall, the CTP has combined processing with the ability to interface to a GPS receiver, an IMU, and a pulse code modulation (PCM) communication link, while providing the capability to support common interfaces including Ethernet and serial interfaces boarding a relatively small-sized, lightweight package.

Valencia, J. Emilio↗

High-Speed Edge-Detecting Line Scan Smart Camera

A high-speed edge-detecting line scan smart camera was developed. The camera is designed to operate as a component in a NASA Glenn Research Center developed inlet shock detection system. The inlet shock is detected by projecting a laser sheet through the airflow. The shock within the airflow is the densest part and refracts the laser sheet the most in its vicinity, leaving a dark spot or shadowgraph. These spots show up as a dip or negative peak within the pixel intensity profile of an image of the projected laser sheet. The smart camera acquires and processes in real-time the linear image containing the shock shadowgraph and outputting the shock location. Previously a high-speed camera and personal computer would perform the image capture and processing to determine the shock location. This innovation consists of a linear image sensor, analog signal processing circuit, and a digital circuit that provides a numerical digital output of the shock or negative edge location. The smart camera is capable of capturing and processing linear images at over 1,000 frames per second. The edges are identified as numeric pixel values within the linear array of pixels, and the edge location information can be sent out from the circuit in a variety of ways, such as by using a microcontroller and onboard or external digital interface to include serial data such as RS-232/485, USB, Ethernet, or CAN BUS; parallel digital data; or an analog signal. The smart camera system can be integrated into a small package with a relatively small number of parts, reducing size and increasing reliability over the previous imaging system..

Prokop, Norman F.↗

Photonics for Space Flight Instruments

For the past 25 years, the National Aeronautics and Space Administration (NASA) Goddard Space Flight Center’s Photonics Group in the Engineering Directorate has been substantially contributing to the flight design, development, production, testing and integration of many science and navigational instruments. The group has an extensive background in screening, qualifying, development and integration of commercial components for spaceflight applications. They have been willing to communicate lessons learned in packaging, part construction, materials selection, testing, and other facets of the design and production process critical to implementation for high-reliability systems. Summarized here is the last ten years of instrumentation development lessons learned and data collected from the subsystems down to the optoelectronic component level.

Spaceflight↗

Ka-Band MMIC Subarray Technology Program (Ka-Mist)

Ka-band monolithic microwave integrated circuit (MMIC) arrays have been considered as having high potential for increasing the capability of space, aircraft, and land mobile communication systems in terms of scan performance, data rate, link margin, and flexibility while offering a significant reduction in size, weight, and power consumption. Insertion of MMIC technology into antenna systems, particularly at millimeter wave frequencies using low power and low noise amplifiers in closed proximity to the radiating elements, offers a significant improvement in the array transmit efficiency, receive system noise figure, and overall array reliability. Application of active array technology also leads to the use of advanced beamforming techniques that can improve beam agility, diversity, and adaptivity to complex signal environments. The objective of this program was to demonstrate the technical feasibility of the 'tile' array packaging architecture at EHF via the insertion of 1990 MMIC technology into a functional tile array or subarray module. The means test of this objective was to demonstrate and deliver to NASA a minimum of two 4 x 4 (16 radiating element) subarray modules operating in a transmit mode at 29.6 GHz. Available (1990) MMIC technology was chosen to focus the program effort on the novel interconnect schemes and packaging requirements rather than focusing on MMIC development. Major technical achievements of this program include the successful integration of two 4 x 4 subarray modules into a single antenna array. This 32 element array demonstrates a transmit EIRP of over 300 watts yielding an effective directive power gain in excess of 55 dB at 29.63 GHz. The array has been actively used as the transmit link in airborne/terrestrial mobile communication experiments accomplished via the ACTS satellite launched in August 1993.

Pottinger, W.↗