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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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NASA NTRS2006

NASA Tech Briefs, March 2006

Topics covered include: Medical Signal-Conditioning and Data-Interface System; Instruments for Reading Direct-Marked Data-Matrix Symbols; Processing EOS MLS Level-2 Data; Ground Processing of Data From the Mars Exploration Rovers; Estimating Total Electron Content Using 1,000+ GPS Receivers; NASA Solar Array Demonstrates Commercial Potential; Improved Control of Charging Voltage for Li-Ion Battery; Programmable Pulse-Position-Modulation Encoder; Wavelength-Agile External-Cavity Diode Laser for DWDM; Pattern-Recognition Processor Using Holographic Photopolymer; Submicrosecond Power-Switching Test Circuit; Three-Function Logic Gate Controlled by Analog Voltage; Integrated System for Autonomous Science; Montage Version 3.0; Utilizing AI in Temporal, Spatial, and Resource Scheduling; Satellite Image Mosaic Engine; Architecture for Control of the K9 Rover; HFGMC Enhancement of MAC/GMC; Automated Activation and Deactivation of a System Under Test; Cleaning Carbon Nanotubes by Use of Mild Oxygen Plasmas; Generating Aromatics From CO2 on Mars or Natural Gas on Earth; Attaching Thermocouples by Peening or Crimping; Heat Treatment of Friction-Stir-Welded 7050 Aluminum Plates; Generating Breathable Air Through Dissociation of N2O; High-Performance Scanning Acousto-Ultrasonic System; Correction for Thermal EMFs in Thermocouple Feedthroughs; Using Quasiparticle Poisoning To Detect Photons; Estimating Resolution Lengths of Hybrid Turbulence Models; Education and Training Module in Alertness Management; Cargo-Positioning System for Next-Generation Spacecraft; Micro-Imagers for Spaceborne Cell-Growth Experiments; Holographic Solar Photon Thrusters; Plasma-Based Detector of Outer-Space Dust Particles; and Generation of Data-Rate Profiles of Ka-Band Deep-Space Links.

Source record↗

NASA NTRS2013

Small Radioisotope Power System Testing at NASA Glenn Research Center

In April 2009, NASA Glenn Research Center (GRC) formed an integrated product team (IPT) to develop a Small Radioisotope Power System (SRPS) utilizing a single Advanced Stirling Convertor (ASC) with passive balancer. A single ASC produces approximately 80 We making this system advantageous for small distributed lunar science stations. The IPT consists of Sunpower, Inc., to provide the single ASC with a passive balancer, The Johns Hopkins University Applied Physics Laboratory (JHUAPL) to design an engineering model Single Convertor Controller (SCC) for an ASC with a passive balancer, and NASA GRC to provide technical support to these tasks and to develop a simulated lunar lander test stand. The single ASC with a passive balancer, simulated lunar lander test stand, and SCC were delivered to GRC and were tested as a system. The testing sequence at GRC included SCC fault tolerance, integration, electromagnetic interference (EMI), vibration, and extended operation testing. The SCC fault tolerance test characterized the SCCs ability to handle various fault conditions, including high or low bus power consumption, total open load or short circuit, and replacing a failed SCC card while the backup maintains control of the ASC. The integrated test characterized the behavior of the system across a range of operating conditions, including variations in cold-end temperature and piston amplitude, including the emitted vibration to both the sensors on the lunar lander and the lunar surface. The EMI test characterized the AC and DC magnetic and electric fields emitted by the SCC and single ASC. The vibration test confirms the SCCs ability to control the single ASC during launch. The extended operation test allows data to be collected over a period of thousands of hours to obtain long term performance data of the ASC with a passive balancer and the SCC. This paper will discuss the results of each of these tests.

Vibration↗

NASA NTRS1982

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.

Woo, D. S.↗

NASA NTRS1993

X-Ray-Diffraction Tests Of Irradiated Electronic Devices: II

Report describes research on use of x-ray diffraction to measure stresses in metal conductors of complementary metal oxide/semiconductor (CMOS) integrated circuits exposed to ionizing radiation. Expanding upon report summarized in "X-Ray-Diffraction Tests Of Irradiated Electronic Devices: I" (NPO-18803), presenting data further suggesting relationship between electrical performances of circuits and stresses and strains in metal conductors.

Shaw, David C.↗

NASA NTRS2016

500 C Electronic Packaging and Dielectric Materials for High Temperature Applications

High-temperature environment operable sensors and electronics are required for exploring the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and application of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high temperature electronics, and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by these high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed. High-temperature environment operable sensors and electronics are required for probing the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and eventual applications of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high electronics and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed.

dielectric performance↗

NASA NTRS1988

Development of gallium arsenide high-speed, low-power serial parallel interface modules: Executive summary

Final report to NASA LeRC on the development of gallium arsenide (GaAS) high-speed, low power serial/parallel interface modules. The report discusses the development and test of a family of 16, 32 and 64 bit parallel to serial and serial to parallel integrated circuits using a self aligned gate MESFET technology developed at the Honeywell Sensors and Signal Processing Laboratory. Lab testing demonstrated 1.3 GHz clock rates at a power of 300 mW. This work was accomplished under contract number NAS3-24676.

Source record↗

NASA NTRS1983

Practical preventive reliability using matrix forms

This paper describes a practical new tool to improve the reliability of equipment. It uses a matrix form to help monitor anticipated component faults precisely. The tool provides the practical measures necessary to generate matrix tables that accurately display all causes of failure and all planned programmatic analyses, tests, processes, and inspections. When completed, the matrix tables give users in-depth visibility of the degree of protection against component failure that is provided by the program's preventive measure plans. The matrix form is an excellent technique for tracking, and thereby influencing, the reliability of nonelectronic spacecraft subsystems or components. No electronic applications have been tried, but the procedure can be useful in the electronics field, e.g., in integrated circuit production planning, and perhaps in process control, inspection or test lines for other electronic components. The drawing of forms, and the recording/manipulation of the data can be computerized.

Johnson, S. A.↗

NASA NTRS2000

Digital Channel Simulator Developed and Tested

The Digital Channel Simulator (DCS) is a real-time test set developed in-house by the NASA Glenn Research Center at Lewis Field that simulates the characteristics of the modulator, demodulator, and transmission medium in a typical communications system to enable controlled laboratory testing of codec pairs. The DCS can support data rates up to 100 megasymbols per second (Msymbols/sec) with symbol sizes up to 10 bits and is compatible with both TTL (transistor transistor logic) and ECL (emitter coupled logic) interfaces. Because of its use of digital integrated circuits (IC's), the DCS offers the user accurate and repeatable testing while maintaining a simple reconfiguration of the modulation scheme and noise characteristics. The PC-based graphical user interface (GUI) assures user friendly operation for configuring, controlling, and monitoring the DCS and system during tests. In a typical communications system, the modulator places a symbol in constellation space and puts it on a carrier to be sent to the demodulator. Because of noise on the channel, the I and Q position in constellation space cannot be recovered exactly, and the received coordinates shift. To mimic this process in the laboratory, the DCS uses a mapper to place the symbol in constellation space. It simulates the shift in coordinates by digitally adding "noise" to the I and Q values. The mapper and noise source are implemented in lookup tables. Modulation schemes and noise characteristics are set by the values loaded in these tables. The mapper also has a pass-through mode to facilitate modulator testing, allowing noise to be added to 8-bit I and Q values of modulated data without a second mapping. To achieve high symbol rates, eight processing circuits are placed in parallel between an ECL demultiplexer and multiplexer. A graphical user interface was developed to calculate, load, and verify the values for the lookup tables. This interface can also be used to debug and verify proper operation of the channel simulator or to control an experiment. Operation of the DCS has been verified through three tests: a low-speed comprehensive system test, a high-speed (20 Msymbols/sec) test of the TTL interface, and a high-speed (100 Msymbols/sec) test of the ECL interface. The DCS is now ready for use by NASA and external customers.

Bizon, Thomas P.↗

NASA NTRS1991

An adjustable RF tuning element for microwave, millimeter wave, and submillimeter wave integrated circuits

Planar RF circuits are used in a wide range of applications from 1 GHz to 300 GHz, including radar, communications, commercial RF test instruments, and remote sensing radiometers. These circuits, however, provide only fixed tuning elements. This lack of adjustability puts severe demands on circuit design procedures and materials parameters. We have developed a novel tuning element which can be incorporated into the design of a planar circuit in order to allow active, post-fabrication tuning by varying the electrical length of a coplanar strip transmission line. It consists of a series of thin plates which can slide in unison along the transmission line, and the size and spacing of the plates are designed to provide a large reflection of RF power over a useful frequency bandwidth. Tests of this structure at 1 GHz to 3 Ghz showed that it produced a reflection coefficient greater than 0.90 over a 20 percent bandwidth. A 2 GHz circuit incorporating this tuning element was also tested to demonstrate practical tuning ranges. This structure can be fabricated for frequencies as high as 1000 GHz using existing micromachining techniques. Many commercial applications can benefit from this micromechanical RF tuning element, as it will aid in extending microwave integrated circuit technology into the high millimeter wave and submillimeter wave bands by easing constraints on circuit technology.

Lubecke, Victor M.↗

NASA NTRS2008

HEMT Amplifiers and Equipment for their On-Wafer Testing

Power amplifiers comprising InP-based high-electron-mobility transistors (HEMTs) in coplanar-waveguide (CPW) circuits designed for operation at frequencies of hundreds of gigahertz, and a test set for onwafer measurement of their power levels have been developed. These amplifiers utilize an advanced 35-nm HEMT monolithic microwave integrated-circuit (MMIC) technology and have potential utility as local-oscillator drivers and power sources in future submillimeter-wavelength heterodyne receivers and imaging systems. The test set can reduce development time by enabling rapid output power characterization, not only of these and similar amplifiers, but also of other coplanar-waveguide power circuits, without the necessity of packaging the circuits.

Fung, King man↗

NASA NTRSDate not supplied

Photonics for Space Flight Instruments

For the past 25 years, the National Aeronautics and Space Administration (NASA) Goddard Space Flight Center’s Photonics Group in the Engineering Directorate has been substantially contributing to the flight design, development, production, testing and integration of many science and navigational instruments. The group has an extensive background in screening, qualifying, development and integration of commercial components for spaceflight applications. They have been willing to communicate lessons learned in packaging, part construction, materials selection, testing, and other facets of the design and production process critical to implementation for high-reliability systems. Summarized here is the last ten years of instrumentation development lessons learned and data collected from the subsystems down to the optoelectronic component level.

Spaceflight↗

NASA NTRS1978

Engineering model 8-cm thruster subsystem

An Engineering Model (EM) 8 cm Ion Thruster Propulsion Subsystem was developed for operation at a thrust level 5 mN (1.1 mlb) at a specific impulse 1 sub sp = 2667 sec with a total system input power P sub in = 165 W. The system dry mass is 15 kg with a mercury-propellant-reservoir capacity of 8.75 kg permitting uninterrupted operation for about 12,500 hr. The subsystem can be started from a dormant condition in a time less than or equal to 15 min. The thruster has a design lifetime of 20,000 hr with 10,000 startup cycles. A gimbal unit is included to provide a thrust vector deflection capability of + or - 10 degrees in any direction from the zero position. The EM subsystem development program included thruster optimization, power-supply circuit optimization and flight packaging, subsystem integration, and subsystem acceptance testing including a cyclic test of the total propulsion package.

Herron, B. G.↗

NASA NTRS1982

Test chips for custom ICs - Six kinds of test structures

Microelectronic test chips contain a number of test structures that are used for a variety of purposes in fabricating integrated circuits. For convenience, their use is divided into six groups: layout-rule evaluating, process-parameter extraction, device-parameter extraction, circuit-parameter extraction, initial-fabrication failure analysis, and reliability failure analysis. A given test structure can be used to gather information in a number of these groups. Examples are given here of the kinds of parameters that can be obtained in each of these groups. A table is included summarizing various device failures common to bulk CMOS and indicating failure mechanisms appearing after wafer fabrication and after stress.

Buehler, M. G.↗

NASA NTRS1985

Latchup in CMOS Integrated Circuits

Sensitivity to ion beams is studied. Latchup effect subject of paper presenting results of testing 19 types of complementary metal-oxide semiconductor (CMOS) chips from six manufacturers. Report gives details of sensitivity of chips to latchup caused by argon and krypton ion beams. Identifies parasitic npnp paths and proides latchup cross section and qualitative explanation of latchup sensitivity for each chip type.

Soliman, K. A.↗

NASA NTRS1986

Simulating Single-Event Upsets in Bipolar RAM's

Simulation technique saves testing. Uses interactive version of SPICE (Simulation Program with Integrated Circuit Emphasis). Device and subcircuit models available in software used to construct macromodel for an integrated bipolar transistor. Time-dependent current generators placed inside transistor macromodel to simulate charge collection from ion track. Significant finding of experiments is standard design practice of reducing power in unaddressed bipolar RAM cell increases sensitivity of cell to single-event upsets.

Zoutendyk, J. A.↗

NASA NTRS1989

SEU In An Advanced Bipolar Integrated Circuit

Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

Zoutendyk, John A.↗

NASA NTRS1989

Characterization of quantum well structures using a photocathode electron microscope

Present day integrated circuits pose a challenge to conventional electronic and mechanical test methods. Feature sizes in the submicron and nanometric regime require radical approaches in order to facilitate electrical contact to circuits and devices being tested. In addition, microwave operating frequencies require careful attention to distributed effects when considering the electrical signal paths within and external to the device under test. An alternative testing approach which combines the best of electrical and optical time domain testing is presented, namely photocathode electron microscope quantitative voltage contrast (PEMQVC).

Spencer, Michael G.↗

NASA NTRS1992

1992 IEEE Annual Conference on Nuclear and Space Radiation Effects, 29th, New Orleans, LA, July 13-17, 1992, Proceedings

The papers presented in this volume provide an overview of recent theoretical and experimental research related to nuclear and space radiation effects. Topics dicussed include single event phenomena, radiation effects in particle detectors and associated electronics for accelerators, spacecraft charging, and space environments and effects. The discussion also covers hardness assurance and testing techniques, electromagnetic effects, radiation effects in devices and integrated circuits, dosimetry and radiation facilities, isolation techniques, and basic mechanisms.

Van Vonno, Nick W.↗