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Data are presented from a range of operating conditions which include background photo flux, operating temperature, and frequency. Each detector is equipped with a load resistor, a cryogenic field effect transistor preamplifier, and a temperature sensor. Data are also presented of detector signal, noise spectra, noise equivalent power, and spectral response.
Remotely-actuated biomedical switching circuit using transistors consumes no power in the off position and can be actuated by a single-frequency telemetry pulse to control implanted instrumentation. Silicon controlled rectifiers permit the circuit design which imposes zero drain on supply batteries when not in use.
This program was directed towards a better understanding of some of the important factors in the performance of infrared detector arrays at low background conditions appropriate for space astronomy. The arrays were manufactured by Aerojet Electrosystems Corporation, Azusa. Two arrays, both bismuth doped silicon, were investigated: an AMCID 32x32 Engineering mosiac Si:Bi accumulation mode charge injection device detector array and a metal oxide semiconductor/field effect transistor (MOS-FET) switched array of 16x32 pixels.
Neither external bias nor energy-storage components required. Three-terminal semiconductor switching circuit features high switching speed, extremely high turnoff safe operating area (area in current-vs-voltage plane), moderately low forward ("on"-state) voltage drop, and efficient utilization of silicon in design of components. Includes gate-turn-off thyristor (GTO) and low-voltage (low-on-resistance) field-effect transistor (FET-1) connected in series to form cascode pair. Made of commercially available, discrete components, as hybrid circuit package or as monolithic integrated circuit.
Recent progress in the development of silicon carbide (SiC) as a semiconductor is briefly reviewed. This material shows great promise towards providing electronic devices that can operate under the high-temperature, high-radiation, and/or high-power conditions where current semiconductor technologies fail. High quality single crystal wafers have become available, and techniques for growing high quality epilayers have been refined to the point where experimental SiC devices and circuits can be developed. The prototype diodes and transistors that have been produced to date show encouraging characteristics, but by the same token they also exhibit some device-related problems that are not unlike those faced in the early days of silicon technology development. Although these problems will not prevent the implementation of some useful circuits, the performance and operating regime of SiC electronics will be limited until these device-related issues are solved.
The first use of a (silicon)/ (heavily doped polysilicon)/ (metal) structure to replace the conventional high-low junction (or back-surface-field, BSF) structure of silicon solar cells is reported. Compared with BSF and back-ohmic-contact control samples, the polysilicon-back solar cells show improvements in red spectral response and open-circuit voltage. Measurement reveals that a decrease in effective surface recombination velocity S is responsible for this improvement. Decreased S results for n-type (Si:As) polysilicon, consistent with past findings for bipolar transistors, and for p-type (Si:B) polysilicon, reported here for the first time. Though the present polysilicon-back solar cells are far from optimal, the results suggest a new class of designs for high efficiency silicon solar cells. Detailed technical reasons are advanced to support this view.
The figure shows one of four solid-state power amplifiers, each capable of generating an output power greater than or equal to 240 mW over one of four overlapping frequency bands from 71 to 106 GHz. (The bands are 71 to 84, 80 to 92, 88 to 99, and 89 to 106 GHz.) The amplifiers are designed for optimum performance at a temperature of 130 K. These amplifiers were developed specifically for incorporation into frequency-multiplier chains in local oscillators in a low-noise, far-infrared receiving instrument to be launched into outer space to make astrophysical observations. The designs of these amplifiers may also be of interest to designers and manufacturers of terrestrial W-band communication and radar systems. Each amplifier includes a set of six high-electron-mobility transistor (HEMT) GaAs monolithic microwave integrated-circuit (MMIC) chips, microstrip cavities, and other components packaged in a housing made from A-40 silicon-aluminum alloy. This alloy was chosen because, for the original intended spacecraft application, it offers an acceptable compromise among the partially competing requirements for high thermal conductivity, low mass, and low thermal expansion. Problems that were solved in designing the amplifiers included designing connectors and packages to fit the available space; designing microstrip signal-power splitters and combiners; matching of impedances across the frequency bands; matching of the electrical characteristics of those chips installed in parallel power-combining arms; control and levelling of output power across the bands; and designing the MMICs, microstrips, and microstrip cavities to suppress tendencies toward oscillation in several modes, both inside and outside the desired frequency bands.
The first use of a (silicon)/heavily doped polysilicon)/(metal) structure to replace the conventional high-low junction or back-surface-field (BSF) structure of silicon solar cells is reported. Compared with BSF and back-ohmic-contact (BOC) control samples, the polysilicon-back solar cells show improvements in red spectral response (RSR) and open-circuit voltage. Measurement reveals that a decrease in effective surface recombination velocity S is responsible for this improvement. Decreased S results for n-type (Si:As) polysilicon, consistent with past findings for bipolar transistors, and for p-type (Si:B) polysilicon, reported here for the first time. Though the present polysilicon-back solar cells are far from optimal, the results suggest a new class of designs for high efficiency silicon solar cells. Detailed technical reasons are advanced to support this view.
A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.
The computer simulation of the electrical behavior of a Gate-Controlled Diode (GCD) fabricated in Silicon-On-Sapphire (SOS) was described. A procedure for determining lifetime profiles from capacitance and reverse current measurements on the GCD was established. Chapter 1 discusses the SOS structure and points out the need of lifetime profiles to assist in device design for GCD's and bipolar transistors. Chapter 2 presents the one-dimensional analytical formula for electrostatic analysis of the SOS-GCD which are useful for data interpretation and setting boundary conditions on a simplified two-dimensional analysis. Chapter 3 gives the results of a two-dimensional analysis which treats the field as one-dimensional until the silicon film is depleted and the field penetrates the sapphire substrate. Chapter 4 describes a more complete two-dimensional model and gives results of programs implementing the model.
Fabrication technique produces field aided lateral PNP transistors compatible with micropower switching circuits. The sub-collector diffusion is performed with phosphorus as the dopant and the epitaxy is grown using the higher temperature silicon tetrachloride process.
The design, wafer-processing techniques, and various measurements which include forward safe operating area, dc characteristics, and switching times are described for a larger-diameter (33) transistor. An improved base contact for equalizing the base-emitter voltage at high currents was developed along with an improved emitter contact preform which increases the silicon area available for current conduction. The electrical performance achieved is consistent with the proposed optimum design.
A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.
This paper is the first to report on a silicon implementation of circutis evolved in simulation. Several circuits were evolved an fabricated in 0.5 micron CMOS process; this paper focuses on results of logical gates evolved at transistor level. It discusses the steps taken in order to increase the chances of robust and portable designs, summarizes the results of characterization tests based on chip measurements, and comments on the performance comparing to simulations.
Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures over the range of -190 C to +225 C in terms of its voltage/current characteristic curves. The test temperatures included +22, -50, -100, -150, -175, -190, +50, +100, +150, +175, +200, and +225 C. Limited thermal cycling testing was also performed on the device. These tests consisted of subjecting the transistor to a total of twelve thermal cycles between -190 C and +225 C. A temperature rate of change of 10 C/min and a soak time at the test temperature of 10 minutes were used throughout this work. Post-cycling measurements were also performed at selected temperatures. In addition, re-start capability at extreme temperatures, i.e. power switched on while the device was soaking for a period of 20 minutes at the test temperatures of -190 C and +225 C, was investigated.
Switching and amplifying characteristics of a newly developed monolithic InGaAs Active Pixel Imager Array are presented. The sensor array is fabricated from InGaAs material epitaxially deposited on an InP substrate. It consists of an InGaAs photodiode connected to InP depletion-mode junction field effect transistors (JFETs) for low leakage, low power, and fast control of circuit signal amplifying, buffering, selection, and reset. This monolithically integrated active pixel sensor configuration eliminates the need for hybridization with silicon multiplexer. In addition, the configuration allows the sensor to be front illuminated, making it sensitive to visible as well as near infrared signal radiation. Adapting the existing 1.55 micrometer fiber optical communication technology, this integration will be an ideal system of optoelectronic integration for dual band (Visible/IR) applications near room temperature, for use in atmospheric gas sensing in space, and for target identification on earth. In this paper, two different types of small 4 x 1 test arrays will be described. The effectiveness of switching and amplifying circuits will be discussed in terms of circuit effectiveness (leakage, operating frequency, and temperature) in preparation for the second phase demonstration of integrated, two-dimensional monolithic InGaAs active pixel sensor arrays for applications in transportable shipboard surveillance, night vision, and emission spectroscopy.
Space radiation effect on MOSFET and metal- silicon nitride-silicon devices, noting protective methods
The Infrared Astronomical Satellite (IRAS) has completed an unbiased all-sky survey at wavelengths from 10 to 100 microns. The design and performance of the focal plane array is described with emphasis on in-orbit measurements of the sensitivity and stability. In the four broad spectral bands centered at 12, 25, 60, and 100 microns, the system noise equivalent flux density (NEFD) values are in Jy/(Square root of Hz), 0.03, 0.025, 0.046, and 0.21, respectively (Jansky = 10 to the -26th W/sq m/Hz). For point sources, a single scan at the survey rate of 3.8 arcmin/s yields limiting flux densities at the 3-sigma confidence level of 0.36, 0.30, 0.39, and 1.2 Jy. The dc stability of the junction field effect transistor (JFET) amplifiers and the excellent off-axis rejection of the telescope permit total flux measurements of extended infrared emission at levels below 6,000,000 Jy/sr. Response of the extrinsic silicon and germanium photo-detectors to ionizing radiation is described.