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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
NASA NTRS2000

Digital Channel Simulator Developed and Tested

The Digital Channel Simulator (DCS) is a real-time test set developed in-house by the NASA Glenn Research Center at Lewis Field that simulates the characteristics of the modulator, demodulator, and transmission medium in a typical communications system to enable controlled laboratory testing of codec pairs. The DCS can support data rates up to 100 megasymbols per second (Msymbols/sec) with symbol sizes up to 10 bits and is compatible with both TTL (transistor transistor logic) and ECL (emitter coupled logic) interfaces. Because of its use of digital integrated circuits (IC's), the DCS offers the user accurate and repeatable testing while maintaining a simple reconfiguration of the modulation scheme and noise characteristics. The PC-based graphical user interface (GUI) assures user friendly operation for configuring, controlling, and monitoring the DCS and system during tests. In a typical communications system, the modulator places a symbol in constellation space and puts it on a carrier to be sent to the demodulator. Because of noise on the channel, the I and Q position in constellation space cannot be recovered exactly, and the received coordinates shift. To mimic this process in the laboratory, the DCS uses a mapper to place the symbol in constellation space. It simulates the shift in coordinates by digitally adding "noise" to the I and Q values. The mapper and noise source are implemented in lookup tables. Modulation schemes and noise characteristics are set by the values loaded in these tables. The mapper also has a pass-through mode to facilitate modulator testing, allowing noise to be added to 8-bit I and Q values of modulated data without a second mapping. To achieve high symbol rates, eight processing circuits are placed in parallel between an ECL demultiplexer and multiplexer. A graphical user interface was developed to calculate, load, and verify the values for the lookup tables. This interface can also be used to debug and verify proper operation of the channel simulator or to control an experiment. Operation of the DCS has been verified through three tests: a low-speed comprehensive system test, a high-speed (20 Msymbols/sec) test of the TTL interface, and a high-speed (100 Msymbols/sec) test of the ECL interface. The DCS is now ready for use by NASA and external customers.

Bizon, Thomas P.↗
NASA NTRS1991

An adjustable RF tuning element for microwave, millimeter wave, and submillimeter wave integrated circuits

Planar RF circuits are used in a wide range of applications from 1 GHz to 300 GHz, including radar, communications, commercial RF test instruments, and remote sensing radiometers. These circuits, however, provide only fixed tuning elements. This lack of adjustability puts severe demands on circuit design procedures and materials parameters. We have developed a novel tuning element which can be incorporated into the design of a planar circuit in order to allow active, post-fabrication tuning by varying the electrical length of a coplanar strip transmission line. It consists of a series of thin plates which can slide in unison along the transmission line, and the size and spacing of the plates are designed to provide a large reflection of RF power over a useful frequency bandwidth. Tests of this structure at 1 GHz to 3 Ghz showed that it produced a reflection coefficient greater than 0.90 over a 20 percent bandwidth. A 2 GHz circuit incorporating this tuning element was also tested to demonstrate practical tuning ranges. This structure can be fabricated for frequencies as high as 1000 GHz using existing micromachining techniques. Many commercial applications can benefit from this micromechanical RF tuning element, as it will aid in extending microwave integrated circuit technology into the high millimeter wave and submillimeter wave bands by easing constraints on circuit technology.

Lubecke, Victor M.↗
NASA NTRS2008

HEMT Amplifiers and Equipment for their On-Wafer Testing

Power amplifiers comprising InP-based high-electron-mobility transistors (HEMTs) in coplanar-waveguide (CPW) circuits designed for operation at frequencies of hundreds of gigahertz, and a test set for onwafer measurement of their power levels have been developed. These amplifiers utilize an advanced 35-nm HEMT monolithic microwave integrated-circuit (MMIC) technology and have potential utility as local-oscillator drivers and power sources in future submillimeter-wavelength heterodyne receivers and imaging systems. The test set can reduce development time by enabling rapid output power characterization, not only of these and similar amplifiers, but also of other coplanar-waveguide power circuits, without the necessity of packaging the circuits.

Fung, King man↗
NASA NTRSDate not supplied

Photonics for Space Flight Instruments

For the past 25 years, the National Aeronautics and Space Administration (NASA) Goddard Space Flight Center’s Photonics Group in the Engineering Directorate has been substantially contributing to the flight design, development, production, testing and integration of many science and navigational instruments. The group has an extensive background in screening, qualifying, development and integration of commercial components for spaceflight applications. They have been willing to communicate lessons learned in packaging, part construction, materials selection, testing, and other facets of the design and production process critical to implementation for high-reliability systems. Summarized here is the last ten years of instrumentation development lessons learned and data collected from the subsystems down to the optoelectronic component level.

Spaceflight↗
NASA NTRS1978

Engineering model 8-cm thruster subsystem

An Engineering Model (EM) 8 cm Ion Thruster Propulsion Subsystem was developed for operation at a thrust level 5 mN (1.1 mlb) at a specific impulse 1 sub sp = 2667 sec with a total system input power P sub in = 165 W. The system dry mass is 15 kg with a mercury-propellant-reservoir capacity of 8.75 kg permitting uninterrupted operation for about 12,500 hr. The subsystem can be started from a dormant condition in a time less than or equal to 15 min. The thruster has a design lifetime of 20,000 hr with 10,000 startup cycles. A gimbal unit is included to provide a thrust vector deflection capability of + or - 10 degrees in any direction from the zero position. The EM subsystem development program included thruster optimization, power-supply circuit optimization and flight packaging, subsystem integration, and subsystem acceptance testing including a cyclic test of the total propulsion package.

Herron, B. G.↗
NASA NTRS1982

Test chips for custom ICs - Six kinds of test structures

Microelectronic test chips contain a number of test structures that are used for a variety of purposes in fabricating integrated circuits. For convenience, their use is divided into six groups: layout-rule evaluating, process-parameter extraction, device-parameter extraction, circuit-parameter extraction, initial-fabrication failure analysis, and reliability failure analysis. A given test structure can be used to gather information in a number of these groups. Examples are given here of the kinds of parameters that can be obtained in each of these groups. A table is included summarizing various device failures common to bulk CMOS and indicating failure mechanisms appearing after wafer fabrication and after stress.

Buehler, M. G.↗
NASA NTRS1985

Latchup in CMOS Integrated Circuits

Sensitivity to ion beams is studied. Latchup effect subject of paper presenting results of testing 19 types of complementary metal-oxide semiconductor (CMOS) chips from six manufacturers. Report gives details of sensitivity of chips to latchup caused by argon and krypton ion beams. Identifies parasitic npnp paths and proides latchup cross section and qualitative explanation of latchup sensitivity for each chip type.

Soliman, K. A.↗
NASA NTRS1986

Simulating Single-Event Upsets in Bipolar RAM's

Simulation technique saves testing. Uses interactive version of SPICE (Simulation Program with Integrated Circuit Emphasis). Device and subcircuit models available in software used to construct macromodel for an integrated bipolar transistor. Time-dependent current generators placed inside transistor macromodel to simulate charge collection from ion track. Significant finding of experiments is standard design practice of reducing power in unaddressed bipolar RAM cell increases sensitivity of cell to single-event upsets.

Zoutendyk, J. A.↗
NASA NTRS1989

SEU In An Advanced Bipolar Integrated Circuit

Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

Zoutendyk, John A.↗
NASA NTRS1989

Characterization of quantum well structures using a photocathode electron microscope

Present day integrated circuits pose a challenge to conventional electronic and mechanical test methods. Feature sizes in the submicron and nanometric regime require radical approaches in order to facilitate electrical contact to circuits and devices being tested. In addition, microwave operating frequencies require careful attention to distributed effects when considering the electrical signal paths within and external to the device under test. An alternative testing approach which combines the best of electrical and optical time domain testing is presented, namely photocathode electron microscope quantitative voltage contrast (PEMQVC).

Spencer, Michael G.↗
NASA NTRS1992

1992 IEEE Annual Conference on Nuclear and Space Radiation Effects, 29th, New Orleans, LA, July 13-17, 1992, Proceedings

The papers presented in this volume provide an overview of recent theoretical and experimental research related to nuclear and space radiation effects. Topics dicussed include single event phenomena, radiation effects in particle detectors and associated electronics for accelerators, spacecraft charging, and space environments and effects. The discussion also covers hardness assurance and testing techniques, electromagnetic effects, radiation effects in devices and integrated circuits, dosimetry and radiation facilities, isolation techniques, and basic mechanisms.

Van Vonno, Nick W.↗
NASA NTRS1993

X-Ray-Diffraction Tests Of Irradiated Electronic Devices: I

X-ray-diffraction tests performed on aluminum conductors in commercial HI1-507A complementary metal oxide/semiconductor (CMOS) integrated-circuit analog multiplexers, both before and after circuits exposed to ionizing radiation from Co(60) source, and after postirradiation annealing at ambient and elevated temperatures. Tests in addition to electrical tests performed to determine effects of irradiation and of postirradiation annealing on electrical operating characteristics of circuits. Investigators sought to determine whether relationship between effects of irradiation on devices and physical stresses within devices. X-ray diffraction potentially useful for nondestructive measurement of stresses.

Shaw, David C.↗
DOE OSTI2024

Beam test performance studies of CMS Phase-2 Outer Tracker module prototypes

A new tracking detector will be installed as part of thePhase-2 upgrade of the CMS detector for the high-luminosity LHC era.This tracking detector includes the Inner Tracker, equipped withsilicon pixel sensor modules, and the Outer Tracker, consisting ofmodules with two parallel stacked silicon sensors. The Outer Trackerfront-end ASICs will be able to correlate hits from chargedparticles in these two sensors to perform on-module discriminationof transverse momenta (p$_{T}$). The p$_{T}$information is generated at a frequency of 40 MHz and will be usedin the Level-1 trigger decision of CMS. Prototypes of theso-called 2S modules were tested at the Test Beam Facility at DESYHamburg between 2019 and 2020. These modules use the finalfront-end ASIC, the CMS Binary Chip (CBC), and for the firsttime the Concentrator Integrated Circuit (CIC), optical readoutand on-module power conversion. In total, seven modules were tested,one of which was assembled with sensors irradiated with protons. Animportant aspect was to show that it is possible to read out modulessynchronously. A cluster hit efficiency of about 99.75 % wasachieved for all modules. The CBC p$_{T}$ discriminationmechanism has been verified to work together with the CIC andoptical readout. The measured module performance meets therequirements for operation in the upgraded CMS tracking detector.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRSDate not supplied

Radiation-Hard Parallel Readout Circuit for Low-Frequency Voltage Signal Measurements

NASA Goddard Space Flight Center (GSFC) has successfully developed and tested a custom-designed low-noise multi-channel digitizer (MCD) application specific integrated circuit (ASIC) for operation in harsh radiation environments. The MCD-ASIC is optimized for low-frequency and low-voltage signal measurements from sensors and transducers. It has 20 input channels where each channel is comprised of auto-zeroed chopper variable-gain amplifier, post amplifier, and a second order ∑∆ modulator. ∑∆ analog-to-digital converter (ADC) relies on oversampling and noise shaping to achieve high-resolution conversion. However, the MCD-ASIC requires digital filtering and decimation to convert the output single bit streams from the ADC to useful data words. A parallel digital platform such as a field-programmable-gate-array (FPGA) is highly suitable to fully leverage the capabilities of the MCD-ASIC. The FPGA controls the MCD-ASIC via serial peripheral interface (SPI) protocol and acquires data from it. A Python-script communicates with the FPGA board through a USB interface on a cross operating platform. Using this architecture, the system is capable of monitoring up to 20 voltage readout channels simultaneously in a real-time manner. Each channel’s parameters can be programmed independently allowing maximum user versatility. In this paper, we present analysis of the analog front-end, the implementation of the digital processing unit on the FPGA, and provide noise performance results from the MCD-ASIC readout.

ASIC↗
NASA NTRS1990

Using advanced microelectronic test chips to qualify ASIC's for space

Qualification procedures for complex integrated circuits are being developed under a U.S. government program known as Qualified Manufacturing Lines (QML). This effort is focused on circuits designed by IC manufacturers and has not addressed application specific IC's (ASIC's) designed at system houses. The qualification procedures described here are intended to be responsive to the needs of system houses who design their own ASIC's and have them fabricated at Silicon foundries. A particular focus of this presentation will be the use of the TID (total Ionizing Dose) Chip to evaluate CMOS foundry processes and to provide parameters for circuit simulators. This chip is under development as a standard chip for qualifying the total dose aspects of ASIC's. The benefits of standardization are that the results will be well understood and easy to interpret. Data is presented and compared for 1.6 micron and 3.0 micron CMOS. The data shows that 1.6 micron CMOS is significantly harder than 3.0 micron CMOS. Two failure modes are explored: (1) the radiation-induced degradation of timing delays; and (2) radiation-induced leakage currents.

Buehler, M. G.↗
NASA NTRS1983

Modeling of single-event upset in bipolar integrated circuits

The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

Zoutendyk, J. A.↗
NASA NTRS1979

Multiple-sample holder for IC testing

Carrousel tray speeds up testing process by feeding mass spectrometer up to 12 sealed integrated circuit packages in rapid succession for analysis of contaminants and total gas composition.

Haack, R. F.↗
NASA NTRS1989

Ka-band MMIC beam steered transmitter array

A 32-GHz six-element linear transmitter array utilizing monolithic microwave integrated circuit (MMIC) phase shifters and power amplifiers was designed and tested as part of the development of a spacecraft array feed for NASA deep-space communications applications. Measurements of the performance of individual phase shifters, power amplifiers, and microstrip radiators were carried out, and electronic beam steering of the linear array was demonstrated. The switched-line phase shifters were accurate to within 7 percent on average and the power amplifier 1-dB compressed output power varied over 0.3 dB. The array had a beamwidth of 7.5 deg and demonstrated acceptable beam steering over + or - 8 deg. From the results, it can be concluded that this MMIC phased array has adequate beam-scanning capability for use in the two-dimensional array. The areas that need to be improved are the efficiency of the MMIC power amplifier and the insertion loss of the MMIC phase shifter.

Rascoe, D. L.↗