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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
NASA NTRS1979

Evaluation of the IMP-16 microprocessor orbit determination system filter

The results of the numerical tests performed in evaluating the interplanetary monitoring platform-16 orbit determination system are presented. The system is capable of performing orbit determination from satellite to satellite tracking data in applications technology satellite range and range rate format. The estimation scheme used is a Kalman filter, sequential (recursive) estimator. Descriptions of the tests performed and tabulations of the numerical results are included.

Shenitz, C. M.↗
NASA NTRS1981

Cosmic ray induced errors in I2L microprocessors and logic devices

Large-scale integrated (LSI) devices fabricated with integrated injection logic (I2L) were studied by both heavy ion experiments and device analysis to determine the upset threshold, the charge collection volumes and ultimately the probability for upset in the galactic cosmic ray spectrum. The devices studied, the SEP9900A, the SBP9989 and the P-Code generator were fabricated by Texas Instruments, Inc.

Price, W. E.↗
NASA NTRS1982

New advances in the partial-reflection-drifts experiment using microprocessors

Improvements to the partial reflection drifts experiment are completed. The results of the improvements include real time processing and simultaneous measurements of the D region with coherent scatter. Preliminary results indicate a positive correlation between drift velocities calculated by both methods during a two day interval. The possibility now exists for extended observations between partial reflection and coherent scatter. In addition, preliminary measurements could be performed between partial reflection and meteor radar to complete a comparison of methods used to determine velocities in the D region.

Ruggerio, R. L.↗
NASA NTRS1983

Digital system upset. The effects of simulated lightning-induced transients on a general-purpose microprocessor

Flight critical computer based control systems designed for advanced aircraft must exhibit ultrareliable performance in lightning charged environments. Digital system upset can occur as a result of lightning induced electrical transients, and a methodology was developed to test specific digital systems for upset susceptibility. Initial upset data indicates that there are several distinct upset modes and that the occurrence of upset is related to the relative synchronization of the transient input with the processing sate of the digital system. A large upset test data base will aid in the formulation and verification of analytical upset reliability modeling techniques which are being developed.

Belcastro, C. M.↗
NASA NTRS1982

A fast microprocessor communication network design for interprocessor communications for an integrated flight control system

A node design with connectivity four is presented whose communication processor handles data at four million bits/sec on each of the four channels into the node, and on each of the four channels out of the node, for a total node capacity of 32 million bits/sec. An integrated flight control system real-time application of this communication network design is discussed. It is shown that such high speed node communication hardware, arranged in the topological configuration of a minimum diameter graph with connectivity four and all links active, has good potential for real time control applications requiring reliability, availability, and survivability characteristics.

Kelly, G. L.↗
NASA NTRS1982

On implementing self-checking microprocessors

A simple and general model of the interfaces and check circuits used for comparing and detecting faults in a pair of 16-bit processors is described, and problems encountered in the application of TI 9900 processors are discussed. The greatest incompatibility is found to lie between the rollback structures of the CPUs and the interface and check logic (ICL) model. The ICL model generates a reset when an error is detected, and a rollback is expected to occur when it is released. The TI 9900 requires a reset of minimum duration, and after release goes through an initialization cycle, obtains rollback parameters from fixed memory locations, and executes the rollback, consistent with the ICL. The ICL is relatively simple, having a complexity equivalent to fewer than 1000 gates.

Rennels, D. A.↗
NASA NTRS1983

ADA and multi-microprocessor real-time simulation

The selection of a high-order programming language for a real-time distributed network simulation is described. The additional problem of implementing a language on a possibly changing network is addressed. The recently designed language ADA (trademarked by DoD) was chosen since it provides the best model of the underlying application to be simulated.

Feyock, S.↗
NASA NTRS1983

Redundant asynchronous microprocessor system for fault tolerant flight control and navigation

Unlike their synchronized counterparts, redundant channels in an asynchronous flight system can, under no-fault conditions, exhibit cross-channel data disparities. Sources of these errors are examined in terms of the general, individual functions of the flight control and navigation application in the asynchronous digital environment. The effects of asynchronism on trajectory programmers, dynamic control algorithms and data reconstruction processes are examined in terms of data skews, data latencies, and clock rate uncertainties. An example is presented in which time corrections are applied to reduce the data disparities. Practical limitations of the approach of the example are discussed.

Dunn, W. R.↗
NASA NTRS1986

Interface Circuits for Self-Checking Microprocessors

Fault-tolerant-microcomputer concept based on enhancing "simple" computer with redundancy and self-checking logic circuits detect hardware faults. Interface and checking logic and redundant processors confer on 16-bit microcomputer ability to check itself for hardware faults. Checking circuitry also checks itself. Concept of self-checking complementary pairs (SCCP's) employed throughout ICL unit.

Rennels, D. A.↗
NASA NTRS1985

High-speed, automatic controller design considerations for integrating array processor, multi-microprocessor, and host computer system architectures

Modern control systems must typically perform real-time identification and control, as well as coordinate a host of other activities related to user interaction, online graphics, and file management. This paper discusses five global design considerations which are useful to integrate array processor, multimicroprocessor, and host computer system architectures into versatile, high-speed controllers. Such controllers are capable of very high control throughput, and can maintain constant interaction with the nonreal-time or user environment. As an application example, the architecture of a high-speed, closed-loop controller used to actively control helicopter vibration is briefly discussed. Although this system has been designed for use as the controller for real-time rotorcraft dynamics and control studies in a wind tunnel environment, the controller architecture can generally be applied to a wide range of automatic control applications.

Jacklin, S. A.↗
NASA NTRS1986

Microprocessor controlled force actuator

The mechanical and electrical design of a prototype force actuator for vibration control of large space structures (LSS) is described. The force actuator is an electromagnetic system that produces a force by reacting against a proof-mass. The actuator has two colocated sensors, a digital microcontroller, and a power amplifier. The total weight of actuator is .998 kg. The actuator has a steady state force output of approximately 2.75 N from approximately 2 Hz to well beyond 1000 Hz.

Zimmerman, D. C.↗
NASA NTRS1987

Microprocessor-Based Valved Controller

New controller simpler, more precise, and lighter than predecessors. Mass-flow controller compensates for changing supply pressure and temperature such as occurs when gas-supply tank becomes depleted. By periodically updating calculation of mass-flow rate, controller determines correct new position for valve and keeps mass-flow rate nearly constant.

Norman, Arnold M., Jr.↗
NASA NTRS1988

A microprocessor-based real-time simulator of a turbofan engine

A real-time digital simulator of a Pratt and Whitney F 100 engine is discussed. This self-contained unit can operate in an open-loop stand-alone mode or as part of a closed-loop control system. It can also be used in control system design and development. It accepts five analog control inputs and its sixteen outputs are returned as analog signals.

Litt, Jonathan S.↗
NASA NTRS1988

Innovative architectures for dense multi-microprocessor computers

The results of a Phase I Small Business Innovative Research (SBIR) project performed for the NASA Langley Computational Structural Mechanics Group are described. The project resulted in the identification of a family of chordal-ring interconnection architectures with excellent potential to serve as the basis for new multimicroprocessor (MMP) computers. The paper presents examples of how computational algorithms from structural mechanics can be efficiently implemented on the chordal-ring architecture.

Donaldson, Thomas↗
NASA NTRS1990

Microprocessor Control For Liquid-Cooled Garment

Automatic control system maintains temperature of water-cooled garment within comfort zone while wearer's level of physical activity varies. Uncomfortable overshoots and undershoots of temperature eliminated. Designed for use in space suit, adaptable to other protective garments and to enclosed environments operating according to similar principles.

Weaver, Charles S.↗
NASA NTRS1991

Microprocessor control of multiple peak power tracking DC/DC converters for use with solar cell arrays

A method and an apparatus is provided for efficiently controlling the power output of a solar cell array string or a plurality of solar cell array strings to achieve a maximum amount of output power from the strings under varying conditions of use. Maximum power output from a solar array string is achieved through control of a pulse width modulated DC/DC buck converter which transfers power from a solar array to a load or battery bus. The input voltage from the solar array to the converter is controlled by a pulse width modulation duty cycle, which in turn is controlled by a differential signal controller. By periodically adjusting the control voltage up or down by a small amount and comparing the power on the load or bus with that generated at different voltage values a maximum power output voltage may be obtained. The system is totally modular and additional solar array strings may be added to the system simply by adding converter boards to the system and changing some constants in the controller's control routines.

Frederick, Martin E.↗