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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

GSFC Cutting Edge Avionics Technologies for Spacecraft

With the launch of NASA's first fiber optic bus on SAMPEX in 1992, GSFC has ushered in an era of new technology development and insertion into flight programs. Predating such programs the Lewis and Clark missions and the New Millenium Program, GSFC has spearheaded the drive to use cutting edge technologies on spacecraft for three reasons: to enable next generation Space and Earth Science, to shorten spacecraft development schedules, and to reduce the cost of NASA missions. The technologies developed have addressed three focus areas: standard interface components, high performance processing, and high-density packaging techniques enabling lower cost systems. To realize the benefits of standard interface components GSFC has developed and utilized radiation hardened/tolerant devices such as PCI target ASICs, Parallel Fiber Optic Data Bus terminals, MIL-STD-1773 and AS1773 transceivers, and Essential Services Node. High performance processing has been the focus of the Mongoose I and Mongoose V rad-hard 32-bit processor programs as well as the SMEX-Lite Computation Hub. High-density packaging techniques have resulted in 3-D stack DRAM packages and Chip-On-Board processes. Lower cost systems have been demonstrated by judiciously using all of our technology developments to enable "plug and play" scalable architectures. The paper will present a survey of development and insertion experiences for the above technologies, as well as future plans to enable more "better, faster, cheaper" spacecraft. Details of ongoing GSFC programs such as Ultra-Low Power electronics, Rad-Hard FPGAs, PCI master ASICs, and Next Generation Mongoose processors.

Luers, Philip J.↗
NASA NTRS1999

Design of the Wind Tunnel Model Communication Controller Board

The NASA Langley Research Center's Wind Tunnel Reinvestment project plans to shrink the existing data acquisition electronics to fit inside a wind tunnel model. Space limitations within a model necessitate a distributed system of Application Specific Integrated Circuits (ASICs) rather than a centralized system based on PC boards. This thesis will focus on the design of the prototype of the communication Controller board. A portion of the communication Controller board is to be used as the basis of an ASIC design. The communication Controller board will communicate between the internal model modules and the external data acquisition computer. This board is based around an Field Programmable Gate Array (FPGA), to allow for reconfigurability. In addition to the FPGA, this board contains buffer Random Access Memory (RAM), configuration memory (EEPROM), drivers for the communications ports, and passive components.

Wilson, William C.↗
NASA NTRS2003

Bandwidth Efficient Baseband Multi-Modulator

The High Rate Baseband Multi-Modulator (HRBM) ASIC is being developed to provide High-speed Bandwidth Efficient Modulations to NASA missions. Bandwidth efficiencies from 2.0 bits/symbol/Hz to 2.75 bits/symbl/Hz are selectable from three CCSDS modulations: Gaussian Minimum Shift Keying (GMSK), Filter Offset Quadrature Phase Shift Keying (Filtered- OQSK) and 8-Phase Shift Keying Trellis Coded Modulation (8-PSK TCM). An FPGA version of the HRBM is developed first to verify the individual modulation designs and characterize timing and performance issues involved with digital baseband modulation synthesis. A Finite Input Response (FIR) filter is included to provided baseband pulse shaping to reduce out-of-band spectral emissions. This is filter is programmable and can be tailored to meet system requirements. The ASIC is targeted to provide up to 600 Mbps throughput and will provide serial as well as parallel input. This paper provides an overview of the technology development and current status.

Fong, Wai↗
NASA NTRS2006

Power Actuation and Switching Module Test Results

The X2000 Power System Electronics (PSE) is a Jet Propulsion Laboratory (JPL) task to develop a new generation of power system building blocks for use on future deep-space missions. The effort includes the development of electronic components and modules that can be used as building blocks in the design of generic spacecraft power systems. All X2000 avionics components and modules are designed for use in centralized or distributed spacecraft architectures. The Power Actuation and Switching Module (PASM) has been developed under the X2000 program. This component enables a modular and scalable design approach for power switching applications, which can result in a wide variety of power switching architectures using this simple building block. The PASM is designed to provide most of the necessary power switching functions of spacecraft for various Deep Space missions including future missions to Mars, comets, Jupiter and its moons. It is fabricated using an ASIC process that is tolerant of high radiation. The development included two application specific integrated circuits (ASICs) and support circuitry all packaged using High Density Interconnect (HDI) technology. It can be operated in series or parallel with other PASMs. It can be used as a high-side or low-side switch and it can drive thruster valves, pyrotechnic devices such as NASA standard initiators, bus shunt resistors, and regular spacecraft component loads. Each PASM contains two independent switches with internal current limiting and over-current trip-off functions to protect the power subsystem from load faults. During turnon and turnoff each switch can limit the rate of current change (di/dt) to a value determined by the user. Three-way majority-voted On/Off commandability and full switch status telemetry (both analog and digital) are built into the module. This paper is a follow up to the one presented at he IECEC 2004 conference that will include the lessons learned and test results from the development.

X2000↗
NASA NTRS2004

Digital circuits using universal logic gates

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Whitaker, Sterling R.↗
NASA NTRS2007

A Radiation Dosimeter Concept for the Lunar Surface Environment

A novel silicon detector configuration for radiation dose measurements in an environment where solar energetic particles are of most concern is described. The dosimeter would also measure the dose from galactic cosmic rays. In the lunar environment a large range in particle flux and ionization density must be measured and converted to dose equivalent. This could be accomplished with a thick (e.g. 2mm) silicon detector segmented into cubic volume elements "voxels" followed by a second, thin monolithic silicon detector. The electronics needed to implement this detector concept include analog signal processors (ASIC) and a field programmable gate array (FPGA) for data accumulation and conversion to linear energy transfer (LET) spectra and to dose-equivalent (Sievert). Currently available commercial ASIC's and FPGA's are suitable for implementing the analog and digital systems.

Adams, James H.↗
NASA NTRS2004

Digital Radar-Signal Processors Implemented in FPGAs

High-performance digital electronic circuits for onboard processing of return signals in an airborne precipitation- measuring radar system have been implemented in commercially available field-programmable gate arrays (FPGAs). Previously, it was standard practice to downlink the radar-return data to a ground station for postprocessing a costly practice that prevents the nearly-real-time use of the data for automated targeting. In principle, the onboard processing could be performed by a system of about 20 personal- computer-type microprocessors; relative to such a system, the present FPGA-based processor is much smaller and consumes much less power. Alternatively, the onboard processing could be performed by an application-specific integrated circuit (ASIC), but in comparison with an ASIC implementation, the present FPGA implementation offers the advantages of (1) greater flexibility for research applications like the present one and (2) lower cost in the small production volumes typical of research applications. The generation and processing of signals in the airborne precipitation measuring radar system in question involves the following especially notable steps: The system utilizes a total of four channels two carrier frequencies and two polarizations at each frequency. The system uses pulse compression: that is, the transmitted pulse is spread out in time and the received echo of the pulse is processed with a matched filter to despread it. The return signal is band-limited and digitally demodulated to a complex baseband signal that, for each pulse, comprises a large number of samples. Each complex pair of samples (denoted a range gate in radar terminology) is associated with a numerical index that corresponds to a specific time offset from the beginning of the radar pulse, so that each such pair represents the energy reflected from a specific range. This energy and the average echo power are computed. The phase of each range bin is compared to the previous echo by complex conjugate multiplication to obtain the mean Doppler shift (and hence the mean and variance of the velocity of precipitation) of the echo at that range.

Berkun, Andrew↗
NASA NTRS2003

SpaceWire Driver Software for Special DSPs

A computer program provides a high-level C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). SpaceWire is a spacecraft-oriented standard for packet-switching data-communication networks that comprise nodes connected through bidirectional digital serial links that utilize low-voltage differential signaling (LVDS). The software is tailored to the SMCS-332 application-specific integrated circuit (ASIC) (also available as the TSS901E), which provides three highspeed (150 Mbps) serial point-to-point links compliant with the proposed Institute of Electrical and Electronics Engineers (IEEE) Standard 1355.2 and equivalent European Space Agency (ESA) Standard ECSS-E-50-12. In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. Routines are provided for interrupt-driven access to the two styles of interface provided by the SMCS: (1) the "word at a time" conventional host interface (HOCI); and (2) a higher performance "dual port memory" style interface (COMI).

Clark, Douglas↗
NASA NTRS2003

NASA Tech Briefs, December 2003

Topics covered include: Organic/Inorganic Hybrid Polymer/Clay Nanocomposites; Less-Toxic Coatings for Inhibiting Corrosion of Aluminum; Liquid Coatings for Reducing Corrosion of Steel in Concrete; Processable Polyimides Containing APB and Reactive End Caps; Rod/Coil Block Copolyimides for Ion-Conducting Membranes; Techniques for Characterizing Microwave Printed Antennas; Cylindrical Antenna With Partly Adaptive Phased-Array Feed; Command Interface ASIC - Analog Interface ASIC Chip Set; Predicting Accumulations of Ice on Aerodynamic Surfaces; Analyzing Aeroelasticity in Turbomachines; Software for Allocating Resources in the Deep Space Network; Expert Seeker; High-Speed Recording of Test Data on Hard Disks; Functionally Graded Nanophase Beryllium/Carbon Composites; Thin Thermal-Insulation Blankets for Very High Temperatures; Aerostructures Test Wing; Flight-Test Evaluation of Flutter-Prediction Methods; Piezoelectrically Actuated Microvalve for Liquid Effluents; Larger-Stroke Piezoelectrically Actuated Microvalve; Innovative, High-Pressure, Cryogenic Control Valve: Short Face-to-Face, Reduced Cost; Safer Roadside Crash Walls Would Limit Deceleration; Improved Interactive Medical-Imaging System; Scanning Microscopes Using X Rays and Microchannels; Slotting Fins of Heat Exchangers to Provide Thermal Breaks; Methane Clathrate Hydrate Prospecting; Automated Monitoring with a BSP Fault-Detection Test; Automated Monitoring with a BCP Fault-Decision Test; Vector-Ordering Filter Procedure for Data Reduction; Remote Sensing and Information Technology for Large Farms; Developments at the Advanced Design Technologies Testbed; Spore-Forming Bacteria that Resist Sterilization; and Acoustical Applications of the HHT Method.

Source record↗
NASA NTRS2013

A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications

Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the new process specific device models. The system has been used in the design of time to digital converters for laser ranging and time-of-flight mass spectrometry to optimize analog, mixed signal and digital circuits such as charge sensitive amplifiers, comparators, delay elements, radiation tolerant dual interlocked (DICE) flip-flops and two of three voter gates.

DuMonthier, Jeffrey↗
NASA NTRS2014

Centering a DDR Strobe in the Middle of a Data Packet

The Orion CEV Northstar ASIC (application- specific integrated circuit) project required a DDR (double data rate) memory bus driver/receiver (DDR PHY block) to interface with external DDR memory. The DDR interface (JESD79C) is based on a source synchronous strobe (DQS\) that is sent along with each packet of data (DQ). New data is provided concurrently with each edge of strobe and is sent irregularly. In order to capture this data, the strobe needs to be delayed and used to latch the data into a register. A circuit solves the need for training a DDR PRY block by incorporating a PVT-compensated delay element in the strobe path. This circuit takes an external reference clock signal and uses the regular clock to calibrate a known delay through a data path. The compensated delay DQS signal is then used to capture the DQ data in a normal register. This register structure can be configured as a FIFO (first in first out), in order to transfer data from the DDR domain to the system clock domain. This design is different in that it does not rely upon the need for training the system response, nor does it use a PLL (phase locked loop) or a DLL (delay locked loop) to provide an offset of the strobe signal. The circuit is created using standard ASIC building blocks, plus the PVT (process, voltage, and temperature) compensated delay line. The design uses a globally available system clock as a reference, alleviating the need to operate synchronously with the remote memory. The reference clock conditions the PVT compensated delay line to provide a pre-determined amount of delay to any data signal that passes through this delay line. The delay line is programmed in degrees of offset, so that one could think of the clock period representing 360deg of delay. In an ideal environment, delaying the strobe 1/4 of a clock cycle (90deg) would place the strobe in the middle of the data packet. This delayed strobe can then be used to clock the data into a register, satisfying setup and hold requirements of the system.

Johnson, Michael↗
NASA NTRS2015

Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

Focal Plane Assembly↗
NASA NTRS2026

The Hyperspectral Microwave Photonic Instrument (HyMPI) and its NEDT Performance

This work presents an overview of a hyperspectral microwave-photonic spectrometer and demonstrates the system end-to-end noise equivalent delta temperature (NEDT) performance. The system aims at augmenting the remote sensing capability from space, with a focus on the Earth’s planetary boundary layer (PBL) thermal microwave (MW) spectral region (0-200 GHz). Combining a Photonic Integrated Circuit (PIC) channelizer and an application-specific integrated circuit (ASIC) spectrometer, the PIC & ASIC (PICASIC) module is capable of processing 40 GHz spectra at hyperspectral (4 MHz) resolution. The photonic technology is agnostic to the spectral region and multiple photonic modules can cover the entire 200 GHz spectrum. Measured results of the end-to-end system NEDT agree with predicted values confirming that the NEDT is primarily dominated by the noise figure of the MW front-end, with the optical link adding no significant noise. The data also demonstrate that a single module enables simultaneous super- and hyper-spectral resolution channel analysis across a 40 GHz range.

spectrometer↗
DOE OSTI2021

hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices

Accessible machine learning algorithms, software, and diagnostic tools for energy-efficient devices and systems are extremely valuable across a broad range of application domains. In scientific domains, real-time near-sensor processing can drastically improve experimental design and accelerate scientific discoveries. To support domain scientists, we have developed hls4ml, an open-source software-hardware codesign workflow to interpret and translate machine learning algorithms for implementation with both FPGA and ASIC technologies. We expand on previous hls4ml work by extending capabilities and techniques towards low-power implementations and increased usability: new Python APIs, quantization-aware pruning, end-to-end FPGA workflows, long pipeline kernels for low power, and new device backends include an ASIC workflow. Taken together, these and continued efforts in hls4ml will arm a new generation of domain scientists with accessible, efficient, and powerful tools for machine-learning-accelerated discovery.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8*10^(-16), significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2026

Design and Modeling of the Charge Readout of a SiMOS Quantum Dot with a Single Electron Transistor and CryoCMOS

Single electron spin qubits trapped in SiMOS quantum dots are a promising technology for scaling to thousand- or million-qubit systems due to their compatibility with mature CMOS manufacturing processes. A readout system that combines a single electron transistor with a custom cryogenic CMOS amplification and digitization chain offers key advantages by avoiding the use of bulky RF components or room-temperature interconnects. We present design techniques and simulation results for an optimized qubit-SET cryoCMOS interface, culminating in the design of the QNDR1 ASIC, the first cryogenic readout ASIC designed under the Quandarum project, which targets the development of a many-channel spin qubit based detector for use in high energy physics.

Quinn, Adam [Fermilab] (ORCID:0009000605056371)↗
DOE OSTI2020

The CLAS12 Micromegas Vertex Tracker

The Micromegas Vertex Tracker was designed to improve upon the tracking capabilities of the baseline design of the CLAS12 spectrometer in Hall~B at Jefferson Laboratory. A Barrel Micromegas Tracker made with six concentric cylinders, each made of three 120$^\circ$-sector tiles, surrounds the Silicon Vertex Tracker, and a Forward Micromegas Tracker composed of 6 disks is placed 30~cm downstream of the liquid-hydrogen target. Both trackers sit in a 5~T solenoid magnetic field. All Micromegas elements are based on resistive technology to withstand luminosities up to $10^{35}$~cm$^{-2}$s$^{-1}$, as well as on bulk technology to enforce gain uniformity and mechanical robustness. Due to the high magnetic field, dedicated electronics have been designed and displaced $\sim$2~m away from the detectors. The electronics readout is based on the DREAM ASICs that allow sustained operation up to 20~kHz trigger rate at the maximum luminosity.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗