Search NASA⌕ Search

SEARCH · Search NASA

Results for “SILICON JUNCTION”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS1995

InGaAlAsPN: A Materials System for Silicon Based Optoelectronics and Heterostructure Device Technologies

A new material system is proposed for silicon based opto-electronic and heterostructure devices; the silicon lattice matched compositions of the (In,Ga,Al)-(As,P)N 3-5 compounds. In this nitride alloy material system, the bandgap is expected to be direct at the silicon lattice matched compositions with a bandgap range most likely to be in the infrared to visible. At lattice constants ranging between those of silicon carbide and silicon, a wider bandgap range is expected to be available and the high quality material obtained through lattice matching could enable applications such as monolithic color displays, high efficiency multi-junction solar cells, opto-electronic integrated circuits for fiber communications, and the transfer of existing 3-5 technology to silicon.

Broekaert, T. P. E.↗
NASA NTRS1967

Thermal and bias cycling stabilizes planar silicon devices

Terminal burn-in or baking step time in the processing of planar silicon devices is extended to reduce their inversion tendencies. The collector-base junction of the device is also cyclically biased during the burn-in.

Harris, R. E.↗
NASA NTRS1976

Determination of surface recombination velocity in heavily doped silicon

A method was developed and successfully tested for the determination of the effective surface recombination velocity of silicon layers doped by diffusion of phosphorus to a level of 10 to the 19th to 10 to the 21st per cu cm. The effective recombination velocity was obtained from the dependence of the electron-beam-induced current on the penetration of the electron beam of a scanning electron microscope. A special silicon diode was constructed which permitted the collection at the p-n junction of the carriers excited by the electron beam. This diode also permitted the study of the effects of surface preparation on the effective surface recombination velocity.

Watanabe, M.↗
NASA NTRS1978

Defect distribution near the surface of electron-irradiated silicon

The surface-defect distributions of electron-irradiated n-type silicon have been investigated using a transient capacitance technique. Schottky, p-n junction, and MOS structures were used in profiling the defect distributions. Surface depletions of defects observed were attributed to the vacancy distribution, but not that of oxygen, and other capture centers' distributions. The vacancy diffusion length at 300 K was estimated to be about 3-6 microns.

Wang, K. L.↗
NASA NTRS1980

The effects of titanium impurities in N/+//P silicon solar cells

Microscopic and electrical measurements were performed to explain the degradation mechanisms associated with the presence of titanium impurities in silicon. The measurements included X-ray topography, transmission electron microscopy, and deep level transient spectroscopy, before and after processing. The results indicated the presence of TiO2 precipitates, the density of which increased after phosphorus diffusion. A majority carrier trapping level was observed in the wafers before processing. It was concluded that 10% of the Ti in the N(+)/P silicon solar cells formed electrically active centers which caused degradation of the cell junction. 14% of the remaining Ti precipitated out as TiO2, forming electrically active defects, which also caused junction degradation.

Salama, A. M.↗
NASA NTRS1980

Development of high efficiency (14 percent) solar cell array module

Most effort was concentrated on development of procedures to provide large area (3 in. diameter) high efficiency (16.5 percent AM1, 28 C) P+NN+ solar cells. Intensive tests with 3 in. slices gave consistently lower efficiency (13.5 percent). The problems were identified as incomplete formation of and optimum back surface field (BSF), and interaction of the BSF process and the shallow P+ junction. The problem was shown not to be caused by reduced quality of silicon near the edges of the larger slices.

Iles, P. A.↗
NASA NTRS1982

Planar multijunction high voltage solar cell chip

A new innovative planar multijunction solar cell chip for concentrated sunlight applications is proposed. The chip consists of many voltage-generating regions, called unit cells, which are connected in series within a single silicon wafer, thereby providing a high open-circuit voltage at multiple sun illumination levels. The unit cells are fabricated on 75 micron thick p-type single crystal silicon substrate. Each chip consists of 1.42 x 9.63 mm n(+)/p collecting junctions on the back of the wafer, while the illuminated front surface area is divided into 0.3 micron deep n(+) regions. The fabrication sequence includes standard degreasing and cleaning procedures, double-sided alignment photomasking, introduction of boron and phosphorus impurities, and photolithography. The open circuit voltage of the chip increased rapidly with illumination up to about 4 AM1 suns, and then began to saturate at the sum of the individual unit cell voltages of 3.5 above 4 AM1 suns. A short circuit density per unit cell of 300 mA/sq cm at 20 AM1 suns was observed.

Valco, G. J.↗
NASA NTRS1987

Silicon radiation detectors with oxide charge state compensation

This paper discusses the use of boron implantation on high resistivity P type silicon before oxide growth to compensate for the presence of charge states in the oxide and oxide/silicon interface. The presence of these charge states on high resistivity P type silicon produces an inversion layer which causes high leakage currents on N(+)P junctions and high surface conductance. Compensating the surface region by boron implantation is shown to result in oxide passivated N(+)P junctions with very low leakage currents and with low surface conductance.

Walton, J. T.↗
NASA NTRS2004

A Wide-Bandwidth, Low-Noise SIS Receiver Design for Millimeter and Submillimeter Wavelengths

In principle, millimeter and submillimeter heterodyne receivers using state-of-the-art SIS detectors are capable of extremely large instantaneous bandwidths with noise temperatures within a few Kelvin of the quantum limit. We are applying modem design tools, such as 3D electromagnetic simulators and Caltech's SuperMix SIS analysis package, to develop a new generation of waveguide SIS mixers with very broad RF and IF bandwidths. Our initial design consists of a double-sideband mixer targeted for the 180- 300 GHz band that uses a single SIS junction excited by a full bandwidth, fixed-tuned waveguide probe on a silicon substrate. The IF output band, limited by the MMIC low-noise IF preamplifier, is 6-18 GHz, providing an instantaneous RF bandwidth of 24 GHz (double-sideband). The SIS mixer conversion loss is predicted to be no more than 1-2 dB (single-sideband) with mixer noise temperatures across the band within 10 Kelvin of the quantum limit. The single-sideband receiver noise temperature goal is 70 Kelvin. The wide instantaneous bandwidth and low noise will result in an instrument capable of a variety of important astrophysical observations beyond the capabilities of current instruments. Lab testing of the receiver will begin in the summer of 2002, and a demonstration on the CSO should occur in the spring of 2003.

Sumner, Matthew↗
NASA NTRS2004

SIS Mixer Design for a Broadband Millimeter Spectrometer Suitable for Rapid Line Surveys and Redshift Determinations

We present some detail of the waveguide probe and SIS mixer chip designs for a low-noise 180-300 GHz double- sideband receiver with an instantaneous RF bandwidth of 24 GHz. The receiver's single SIS junction is excited by a broadband, fixed-tuned waveguide probe on a silicon substrate. The IF output is coupled to a 6-18 GHz MMIC low- noise preamplifier. Following further amplification, the output is processed by an array of 4 GHz, 128-channel analog autocorrelation spectrometers (WASP 11). The single-sideband receiver noise temperature goal of 70 Kelvin will provide a prototype instrument capable of rapid line surveys and of relatively efficient carbon monoxide (CO) emission line searches of distant, dusty galaxies. The latter application's goal is to determine redshifts by measuring the frequencies of CO line emissions from the star-forming regions dominating the submillimeter brightness of these galaxies. Construction of the receiver has begun; lab testing should begin in the fall. Demonstration of the receiver on the Caltech Submillimeter Observatory (CSO) telescope should begin in spring 2003.

Rice, F.↗
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
NASA NTRS1990

Silicon carbide semiconductor device fabrication and characterization

A number of basic building blocks i.e., rectifying and ohmic contacts, implanted junctions, MOS capacitors, pnpn diodes and devices, such as, MESFETs on both alpha and beta SiC films were fabricated and characterized. Gold forms a rectifying contact on beta SiC. Since Au contacts degrade at high temperatures, these are not considered to be suitable for high temperature device applications. However, it was possible to utilize Au contact diodes for electrically characterizing SiC films. Preliminary work indicates that sputtered Pt or Pt/Si contacts on beta SiC films are someways superior to Au contacts. Sputtered Pt layers on alpha SiC films form excellent rectifying contacts, whereas Ni layers following anneal at approximately 1050 C provide an ohmic contact. It has demonstrated that ion implantation of Al in substrates held at 550 C can be successfully employed for the fabrication of rectifying junction diodes. Feasibility of fabricating pnpn diodes and platinum gated MESFETs on alpha SiC films was also demonstrated.

Davis, R. F.↗
NASA NTRS1972

AC impedance of silicon solar cells.

The equivalent source impedance of a solar array is an important parameter in the design and analysis of solar array power conditioning equipment. Laboratory impedance tests have been performed on individual silicon solar cells and the test results have been correlated with P-N junction theory as developed by Shockley. The impedance has been broken into resistive and reactive components. The impedance has been expressed as a function of DC operating point and frequency. A practical application of the individual cell characteristics is presented in a solar array simulator design.

Zerbel, D. W.↗
NASA NTRS1987

Optical response at 10.6 microns in tungsten silicide Schottky barrier diodes

Optical response to radiation at a wavelength of 10.6 microns in tungsten silicide-silicon Schottky barrier diodes has been observed. Incident photons excite electrons by means of junction plasmon assisted inelastic electron tunneling. At 78 K, a peak in the second derivative of current versus junction bias voltage was observed at a voltage corresponding to the energy of photons having a wavelength of 10.6 microns. This peak increased with increasing incident laser power, saturating at the highest laser powers investigated.

Kumar, Sandeep↗
NASA NTRS1994

Making CoSi(2) Layers By Ion Implantation

Monolithic photovoltaic batteries containing vertical cells include buried CoSi(2) contact layers. Vertical-junction photovoltaic cells in series fabricated in monolithic structure. N- and p-doped silicon layers deposited epitaxially. The CoSi(2) layers, formed by ion implantation and annealing, serve as thin, low-resistance ohmic contacts between cells.

Namavar, Fereydoon↗
NASA NTRS2004

A Two-Dimensional, Semiconducting Bolometer Array for HAWC

The Stratospheric Observatory For Infrared Astronomy's (SOFIA's) High resolution Airborne Wideband Camera (HAWC) will use an ion-implanted silicon bolometer array developed at NASA s Goddard Space Flight Center (GSFC). The GSFC Pop-Up Detectors (PUDs) use a unique folding technique to enable a 12 x 32 element closepacked array of bolometers with a filling factor greater than 95%. The HAWC detector uses a resistive metal film on silicon to provide frequency independent, approx. 50% absorption over the 40 - 300 micron band. The silicon bolometers are manufactured in 32-element rows within silicon frames using Micro Electro Mechanical Systems (MEMS) silicon etching techniques. The frames are then cut, "folded", and glued onto a metallized, ceramic, thermal bus "bar". Optical alignment using micrometer jigs ensures their uniformity and correct placement. The rows are then stacked side-by-side to create the final 12 x 32 element array. A kinematic Kevlar suspension system isolates the 200 mK bolometer cold stage from the rest of the 4K detector housing. GSFC - developed silicon bridge chips make electrical connection to the bolometers, while maintaining thermal isolation. The Junction Field Effect Transistor (JFET) preamplifiers for all the signal channels operate at 120 K, yet they are electrically connected and located in close proximity to the bolometers. The JFET module design provides sufficient thermal isolation and heat sinking for these, so that their heat is not detected by the bolometers. Preliminary engineering results from the flight detector dark test run are expected to be available in July 2004. This paper describes the array assembly and mechanical and thermal design of the HAWC detector and the JFET module.

Voellmer, George M.↗