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Report describes one-year research effort in VLSL fabrication. Four activities are described: theoretical study of two-dimensional diffusion in SOS (silicon-on-sapphire); setup of sputtering system, furnaces, and photolithography equipment; experiments on double layer metal; and investigation of two-dimensional modeling of MOSFET's (metal-oxide-semiconductor field-effect transistors).
A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.
A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.
New fabrication method produces pinhole-free film of cobalt silicide on silicon substrate. In new method, cobalt and silicon evaporated from electron-beam sources onto substrate of silicon having <111> crystal orientation. Materials deposited in stoichiometric ratio of two silicon atoms to one of cobalt, yielding single-crystal CoSi2 film 5 to 10 nm thick. Layer of amorphous silicon 1 to 2 nm thick deposited on CoSi2. Specimen then annealed at 550 degree C for 10 min. Absence of pinholes critical to operation of multilayer devices employing CoSi2 layers, such as metal base transistor.
The reliability of crystalline silicon modules has been brought to a high level with lifetimes approaching 20 years, and excellent industry credibility and user satisfaction. The transition from crystalline modules to thin film modules is comparable to the transition from discrete transistors to integrated circuits. New cell materials and monolithic structures will require new device processing techniques, but the package function and design will evolve to a lesser extent. Although there will be new encapsulants optimized to take advantage of the mechanical flexibility and low temperature processing features of thin films, the reliability and life degradation stresses and mechanisms will remain mostly unchanged. Key reliability technologies in common between crystalline and thin film modules include hot spot heating, galvanic and electrochemical corrosion, hail impact stresses, glass breakage, mechanical fatigue, photothermal degradation of encapsulants, operating temperature, moisture sorption, circuit design strategies, product safety issues, and the process required to achieve a reliable product from a laboratory prototype.
For wireless power transmission using microwave energy, very efficient conversion of the DC power into microwave power is extremely important. Class E amplifiers have the attractive feature that they can, in theory, be 100% efficient at converting, DC power to RF power. Aluminum gallium nitride (AlGaN) semiconductor material has many advantageous properties, relative to silicon (Si), gallium arsenide (GaAs), and silicon carbide (SiC), such as a much larger bandgap, and the ability to form AlGaN/GaN heterojunctions. The large bandgap of AlGaN also allows for device operation at higher temperatures than could be tolerated by a smaller bandgap transistor. This could reduce the cooling requirements. While it is unlikely that the AlGaN transistors in a 5.8 GHz class E amplifier can operate efficiently at temperatures in excess of 300 or 400 C, AlGaN based amplifiers could operate at temperatures that are higher than a GaAs or Si based amplifier could tolerate. Under this program, AlGaN microwave power HFETs have been fabricated and characterized. Hybrid class E amplifiers were designed and modeled. Unfortunately, within the time frame of this program, good quality HFETs were not available from either the RSC laboratories or commercially, and so the class E amplifiers were not constructed.
A submillimeter-wave monolithic integrated- circuit (S-MMIC) amplifier has been designed and fabricated using an indium phosphide (InP) 35-nm gate-length high electron mobility transistor (HEMT) device, developed at Northrop Grumman Corporation. The HEMT device employs two fingers each 15 micrometers wide. The HEMT wafers are grown by molecular beam epitaxy (MBE) and make use of a pseudomorphic In0.75Ga0.25As channel, a silicon delta-doping layer as the electron supply, an In0.52Al0.48As buffer layer, and an InP substrate. The three-stage design uses coplanar waveguide topology with a very narrow ground-to-ground spacing of 14 micrometers. Quarter-wave matching transmission lines, on-chip metal-insulator-metal shunt capacitors, series thin-film resistors, and matching stubs were used in the design. Series resistors in the shunt branch arm provide the basic circuit stabilization. The S-MMIC amplifier was measured for S-parameters and found to be centered at 320 GHz with 13-15-dB gain from 300-345 GHz. This chip was developed as part of the DARPA Submillimeter Wave Imaging Focal Plane Technology (SWIFT) program (see figure). Submillimeter-wave amplifiers could enable more sensitive receivers for earth science, planetary remote sensing, and astrophysics telescopes, particularly in radio astronomy, both from the ground and in space. A small atmospheric window at 340 GHz exists and could enable ground-based observations. However, the submillimeter-wave regime (above 300 GHz) is best used for space telescopes as Earth s atmosphere attenuates most of the signal through water and oxygen absorption. Future radio telescopes could make use of S-MMIC amplifiers for wideband, low noise, instantaneous frequency coverage, particularly in the case of heterodyne array receivers.
X-ray detector array yields mosaic image of object emitting 1- to 30-keV range fabricated from n-doped silicon wafer. In proposed fabrication technique, thin walls of diffused n+ dopant divide wafer into pixels of rectangular cross section, each containing central electrode of thermally migrated p-type metal. This pnn+ arrangement reduces leakage current by preventing transistor action caused by pnp structure of earlier version.
This innovation represents a method and circuit realization of a system designed to make in-situ measurements of test solar-cell operational parameters on orbit using readily available high-temperature and high-ionizing-radiation- tolerant electronic components. This innovation enables on-orbit in-situ solar-array health monitoring and is in response to a need recognized by the U.S. Air Force for future solar arrays for unmanned spacecraft. This system can also be constructed out of commercial-grade electronics and can be embedded into terrestrial solar power system as a diagnostics instrument. This innovation represents a novel approach to I-V curve measurement that is radiation and temperature hard, consumes very few system resources, is economical, and utilizes commercially available components. The circuit will also operate at temperatures as low as 55 C and up to +225 C, allowing it to reside close to the array in direct sunlight. It uses a swept mode transistor functioning as a resistive load while utilizing the solar cells themselves as the biasing device, so the size of the instrument is small and there is no danger of over-driving the cells. Further, this innovation utilizes nearly universal spacecraft bus resources and therefore can be readily adapted to any spacecraft bus allowing for ease of retrofit, or designed into new systems without requiring the addition of infrastructure. One unique characteristic of this innovation is that it effects the measurement of I-V curves without the use of large resistor arrays or active current sources normally used to characterize cells. A single transistor is used as a variable resistive load across the cell. This multi-measurement instrument was constructed using operational amplifiers, analog switches, voltage regulators, MOSFETs, resistors, and capacitors. The operational amplifiers, analog switches, and voltage regulators are silicon-on-insulator (SOI) technology known for its hardness to the effects of ionizing radiation. The SOI components used can tolerate temperatures up to 225 C, which gives plenty of thermal headroom allowing this circuit to perhaps reside in the solar cell panel itself where temperatures can reach over 100 C.
Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.
Silicon carbide (SiC) power devices have demonstrated many performance advantages over their silicon (Si) counterparts. As the inherent material limitations of Si devices are being swiftly realized, wide-band-gap (WBG) materials such as SiC have become increasingly attractive for high power applications. In particular, SiC power metal oxide semiconductor field effect transistors' (MOSFETs) high breakdown field tolerance, superior thermal conductivity and low-resistivity drift regions make these devices an excellent candidate for power dense, low loss, high frequency switching applications in extreme environment conditions. In this paper, a novel power processing unit (PPU) architecture is proposed utilizing commercially available 4H-SiC power MOSFETs from CREE Inc. A multiphase straight boost converter topology is implemented to supply up to 10 kilowatts full-scale. High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) characterization is performed to evaluate the long-term reliability of both the gate oxide and the body diode of the SiC components. Finally, susceptibility of the CREE SiC MOSFETs to damaging effects from heavy-ion radiation representative of the on-orbit galactic cosmic ray environment are explored. The results provide the baseline performance metrics of operation as well as demonstrate the feasibility of a hard-switched PPU in harsh environments.
Characterization results of a MOS controlled thyristor (MCTA60P60) are presented. This device is rated for 60A and for an anode to cathode voltage of -600 V. As discussed in the last report, the MCT failed during 500 V leakage tests at 200 C. In contrast to the BJT (bipolar junction transistor), MOSFET, and IGBT (insulated gate bipolar transistor) devices tested, the breakdown voltage of the MCT decreases significantly with increasing temperature.
The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.
Markets, applications, and production techniques for Siemens process-produced polycrystalline silicon are surveyed. It is noted that as of 1982 a total of six Si materials suppliers were servicing a worldwide total of over 1000 manufacturers of Si-based devices. Besides solar cells, the Si wafers are employed for thyristors, rectifiers, bipolar power transistors, and discrete components for control systems. An estimated 3890 metric tons of semiconductor-grade polycrystalline Si will be used in 1982, and 6200 metric tons by 1985. Although the amount is expected to nearly triple between 1982-89, research is being carried out on the formation of thin films and ribbons for solar cells, thereby eliminating the waste produced in slicing Czolchralski-grown crystals. The free-world Si production in 1982 is estimated to be 3050 metric tons. Various new technologies for the formation of polycrystalline Si at lower costs and with less waste are considered. New entries into the industrial Si formation field are projected to produce a 2000 metric ton excess by 1988.
The development of arrays of infrared bolometers that are suitable for use in the Far Infrared and Submillimeter Telescope (FIRST) mission is reported. The array architecture is based on the silicon nitride micromesh bolometer currently baselined for use in the case of the Planck mission. This architecture allows each pixel to be efficiently coupled to one or both polarizations and to one or more spatial models of radiation. Micromesh structures are currently being developed, coupled with transistor-edge sensors and read out by a SQUID amplifier. If these devices are successful, then the relatively large cooling power available at 300 mK may enable a SQUID-based multiplexer to be integrated on the same wafer as the array, creating a monolithic, fully multiplexed, 2D array with relatively few connections to the sub-Kelvin stage.
New family of fast-recovery high-voltage power diodes compatible with D60T and D7ST transistors developed. Have wide range of applications in spacecraft and aircraft electrical distribution equipment, dc/dc inverters, and ac motor controllers for high-horsepower electric motors operating from 480-volt ac lines. Fast-Recovery 1,200-V Power Diodes use chip of hexagonal geometry to maximize effective silicon area.
We report for the first time the successful integration of Strontium-Bismuth-Tantalate ferroelectric capacitors on an SOI Substrate. We have verified that the unique processing requirements of SBT capacitors does not affect the properties of the surrounding FD-SOI transistors, and, conversely, we have verified that the SOI processing does not affect the quality of the SBT capacitors.
The solar cell module process development activities in the areas of surface preparation are presented. The process step development was carried out on texture etching including the evolution of a conceptual process model for the texturing process; plasma etching; and diffusion studies that focused on doped polymer diffusion sources. Cell processing was carried out to test process steps and a simplified diode solar cell process was developed. Cell processing was also run to fabricate square cells to populate sample minimodules. Module fabrication featured the demonstration of a porcelainized steel glass structure that should exceed the 20 year life goal of the low cost silicon array program. High efficiency cell development was carried out in the development of the tandem junction cell and a modification of the TJC called the front surface field cell. Cell efficiencies in excess of 16 percent at AM1 have been attained with only modest fill factors. The transistor-like model was proposed that fits the cell performance and provides a guideline for future improvements in cell performance.