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Results are given of SEU measurements on 256K dynamic RAMs with on-chip error correction. They are claimed to be the first ever reported. A (12/8) Hamming error-correcting code was incorporated in the layout. Physical separation of the bits in each code word was used to guard against multiple bits being disrupted in any given word. Significant reduction in observed errors is reported.
Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.
A single chip, fixed frequency suboptimum bit synchronizer design which was implemented utilizing a programmable logic device is described. The bit synchronizer is modeled after a digital transition tracking loop for symbol estimation and employs a first-order incremental phase modulator for closed-loop symbol synchronization. The BER and tracking performance is modeled and compared to optimum designs. The bit synchronizer was developed for the Space Shuttle.
An array processing chip integrating 128 bit-serial processing elements (PEs) on a single die is discussed. Each PE has a 16-function logic unit, a single-bit adder, a 32-b variable-length shift register, and 1 kb of local RAM. Logic in each PE provides the capability to mask PEs individually. A modified grid interconnection scheme allows each PE to communicate with each of its eight nearest neighbors. A 32-b bus is used to transfer data to and from the array in a single cycle. Instruction execution is pipelined, enabling all instructions to be executed in a single cycle. The 1-micron CMOS design contains over 1.1 x 10 to the 6th transistors on an 11.0 x 11.7-mm die.
While the pixel size in a standard multianode microchannel array (MAMA) photon-counting detector is determined by the spacing of the anode array, the factor most fundamentally limiting pixel resolution is the spacing of the channels in the microchannel plate. Detector resolution can be improved by means of digitization followed by a centroiding procedure. The decoding hardware and the techniques for enhanced pixel resolution are presently discussed with a view to the factors of speed and complexity. A single-chip CMOS gate-array implementation of the decoder is devised and compared with existing multichip decoders' performance.
The JPL CRRES chip was designed and fabricated in 1985 and included in the CRRES MEP. MOSFET Matrix results show the effect of shielding on radiation-induced MOSFET threshold voltage shifts and channel mobility degradation. Shielded (middle board) MOSFETs have a threshold-voltage damage factor that is approximately three orders of magnitude smaller than would be estimated from Co-60 ground tests. Unshielded (outer board) MOSFETs have a threshold-voltage damage factor that would be estimated from Co-60 ground tests. Temperature swings as large as 23 C with a 22.5 orbit periodicity affected the MOSFET data and were removed from the data in order to reveal the radiation effects. This experiment demonstrated the feasibility of characterizing MOSFETs in a matrix, thus reducing the complexity and mass of the experiment.
Custom-made single-chip complementary metal-oxide semiconductor (CMOS) integrated circuit designed to reveal effects of ionizing radiation on itself and similar integrated circuits. Potential terrestrial use: safety-oriented monitoring of ionizing radiation at nuclear powerplants, nuclear-waste sites, and the like.
A two- and three-dimensional multi-chip module technology was developed in response to the continuum in demand for increased performance in electronic systems, as well as the desire to reduce the size, weight, and power of space systems. Though developed to satisfy the needs of military programs, such as the Strategic Defense Initiative Organization, the technology, referred to as High Density Interconnect, can also be advantageously exploited for a wide variety of commercial applications, ranging from computer workstations to instrumentation and microwave telecommunications. The robustness of the technology, as well as its high performance, make this generality in application possible. More encouraging is the possibility of this technology for achieving low cost through high volume usage.
Recent developments in materials technology now make it possible to fabricate nonthermal thin-film radioisotopic energy converters (REC) with a specific power of 24 W/kg and a 10 year working life at 5 to 10 watts. This creates applications never before possible, such as placing the power supply directly on integrated circuit chips. The efficiency of the REC is about 25 percent which is two to three times greater than the 6 to 8 percent capabilities of current thermoelectric systems. Radio isotopic energy converters have the potential to meet many future space power requirements for a wide variety of applications with less mass, better efficiency, and less total area than other power conversion options. These benefits result in significant dollar savings over the projected mission lifetime.
Eddy current probes have been used for many years for numerous sensing applications including crack detection in metals. However, these applications have traditionally used the eddy current effect in the form of a physically wound single or different probe pairs which of necessity must be made quite large compared to microelectronics dimensions. Also, the traditional wound probe can only take a point reading, although that point might include tens of individual cracks or crack arrays; thus, conventional eddy current probes are beset by two major problems: (1) no detailed information can be obtained about the crack or crack array; and (2) for applications such as quality assurance, a vast amount of time must be taken to scan a complete surface. Laboratory efforts have been made to fabricate linear arrays of single turn probes in a thick film format on a ceramic substrate as well as in a flexible cable format; however, such efforts inherently suffer from relatively large size requirements as well as sensitivity issues. Preliminary efforts to fully extend eddy current probing from a point or single dimensional level to a two dimensional micro-eddy current format on a silicon chip, which might overcome all of the above problems, are presented.
A highly efficient error correcting code has been selected by NASA as a CCSDS standard: the 16 symbol error correcting Reed Solomon code. A VLSI implementation of this decoder is described in this paper. A total of 4 full custom VLSI chips are needed that correct data in real time at an sustained rate of up to 80 Mbits/second.
A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.
The contractor attended the critical design review and evaluated the presentations of other team members and presented data on the inductive edge sensor. The prototype micro-chip inductive edge sensor was evaluated, and devices were found to have a number of characteristics which made them unsuitable for installation on the seven segment demonstrator. The amplifier bandwidth was too low, the output drive current was too small, and there is an interaction between the digital circuitry and the amplifier that causes the amplifier to stop functioning. Therefore, the inductive edge sensors were not installed on the seven segment demonstrator. The contractor has participated in instruction, problem analysis, and provided technical assistance to NASA and its contractors for the development of 8 hexagonal mirror faceplates with electronics and edge sensors.
The results of a study carried out in order to manufacture and verify the quality of chip-on-board (COB) packaging technology are presented. The COB, designed for space applications, was tested under environmental stresses, temperature cycling, and temperature-humidity-bias. Both robustness in space applications and in environmental protection on the ground-complete reliability without hermeticity were searched for. The epoxy-parylene combinations proved to be superior to other materials tested.
Recently, Jet Propulsion Laboratory has invented and developed a miniature optical microscope, microscope-on-chip using micro-channel and solid state image sensors. It is lightweight, low-power, fast speed instrument, it has no image lens, does not need focus adjustment, and the total mass is less than 100g. A prototype has been built and demonstrated at JPL.
The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. In the process of building the Consortium CSP test vehicles, many challenges were identified regarding various aspects of technology implementation. This paper will present our experience in the areas of technology implementation challenges, including design and building both standard and microvia boards, and assembly of two types of test vehicles. We also discuss the most current package isothermal aging to 2,000 hours at 100 C and 125 C and thermal cycling test results to 1,700 cycles in the range of -30 to 100 C.
Many aspects of chip scale package (CSP) technology, with focus on assembly reliability characteristics, are being investigated by the JPL-led consortia. Three types of test vehicles were considered for evaluation and currently two configurations have been built to optimize attachment processes. These test vehicles use numerous package types. To understand potential failure mechanisms of the packages, particularly solder ball attachment, the grid CSPs were subjected to environmental exposure. Package I/Os ranged from 40 to nearly 300. This paper presents both as assembled, up to 1, 000 hours of isothermal aging shear test results and photo micrographs, and tensile test results before and after 1,500 cycles in the range of -30/100 C for CSPs. Results will be compared to BGAs with the same the same isothermal aging environmental exposures.
Four Free-Flying Magnetometers (FFMs), developed at the Jet Propulsion Laboratory (JPL) for the Enstrophy mission, were successfully deployed from the payload of a sounding rocket launched from Poker Flats, Alaska on February 11, 1999. The FFMs functioned successfully by synchronously measuring the vector magnetic field at 4 points separate from the payload and at relative distances up to 3 km, and communicated their data, in bursts, to the ground. This is the first time synchronized in-situ multipoint measurements of the Earth's magnetic field utilizing miniature spin-stabilized "sensorcraft" have been performed. The data they provided have enabled, for the first time, the direct measure of field-aligned current density and are enabling new science by determining the fine-scale structure of the currents in the Earth's ionosphere involved in the production of aurora. These proof-of-concept "hockey puck" (80 mm diameter, 38 mm height, 250 gram mass) FFMs were built using off-the-shelf commercial, industrial, and military grade surface-mount electronic components. Radiation-hard electronics was not required for the Enstrophy mission's short sub-orbital flight. The successful design, implementation, and flight demonstration of this 1st generation FFM design has provided a solid base for further development of a 2nd generation FFM design for planetary science applications. A reliable ultra-miniature radiation-hard 2nd-generation FFM utilizing System-On-A-Chip (SOAC) technologies is proposed. This design would be targeted for long-term planetary missions to investigate magnetospheric field configurations in regions having small-scale structure and to separate spatial and temporal variations. A fleet of short-lived (expendable) FFMs would be deployed into a targeted region to gather multiprobe vector magnetic field data. The FFMs would be ejected from a parent spacecraft at a speed of a few m/sec and would cover spatial volumes of order tens of kilometers for times of order one hour. The parent spacecraft would carry a sufficient number of FFMs for multiple deployments. Additional information is contained in the original extended abstract.